jeffrogers1113
New Member
I have a 9 stage Finite State Diagram for a MIPS processor, and I have the following assignment:
It is desired to include new instructions into this MIPS subset. For each of the candidate new instructions listed below, indicate:
I. what new control signals (if any) would be needed.
II. what new states (if any) would be needed for the FSM
III. the appropriate transitions into and from any new states including the conditions that would trigger the transition
The candidate new instructions are:
a) (15) addi (add immediate)
b) (15) xor (exclusive-OR)
c) (15) srl (shift right logical)
Can anybody get me going in the right direction? I can provide the FSM diagram if needed.
It is desired to include new instructions into this MIPS subset. For each of the candidate new instructions listed below, indicate:
I. what new control signals (if any) would be needed.
II. what new states (if any) would be needed for the FSM
III. the appropriate transitions into and from any new states including the conditions that would trigger the transition
The candidate new instructions are:
a) (15) addi (add immediate)
b) (15) xor (exclusive-OR)
c) (15) srl (shift right logical)
Can anybody get me going in the right direction? I can provide the FSM diagram if needed.