Reading more than one memory location at a time was also a technique used, when memory access was much slower than processor speed, but optimum processor performance was needed (can you say pre-cache?). I worked with some specialty processors that accessed memory, 2 word lengths at a time. It had special internal registers to store the extra memory fetch, and processed the instructions while preforming the next memory fetch. This setup allowed the processor to work at top speed and not have to wait on memory reads.
Dialtone