MC & LATCH

[athlon11]

Hi everybody…

I have a circuit diagram of a control board, I see the MC (8051-Based MC) is connected to a Latch (Octal D LATCH-74HCT573) through PORT00.0 to P0.7 (AD0 to AD7)

How does those 2 components communicate and work together in general, how do we choose the right Latch to put with our MC?

Any links also to similar issues would be of great help.

Thank u in adv.

 

[williB]

https://www.electro-tech-online.com/custompdfs/2005/02/74LS573.pdf
the answer is in the latch.. in the truth table or function table as they call it,when latch enable is high it will pass the value of the input to the output..
when latch enable is is low the 573 latches the value that was previously on the inputs..
the fourth possible condition or state is when output enable is high, when this occurs the output is in high impedence state Z .. in this condition the latch enable and D inputs are Dont Care..

 

[bmcculla]

If its an 8051 with AD labled pins the latch is probably for a multiplexed external data bus.

The multiplexed bus lets you have a 16 bit address and 8 bit data with only 16 pins. They do this by sharing the pins AD0-7 between both address and data. The label AD stands for Address/Data line. The upper bus lines are just Address lines so they are just A8-15.

The bus cycle works like this: First the 16 bit address is output on all 16 pins and ALE (Address Latch Enable) is set which causes the latch to store the 8 bits AD0-7 on its ouput pins. The bus then puts the data bits on AD0-7 and strobes the WR or RD pin to do a read or write to the bus. When the buss is strobed AD0-7 are the data bits the latch outputs are address bits 0-7 and A8-15 are address bits 8-15.

Hope this helps
Brent

 

[athlon11]

mc

Thank u people (williB , Bmcculla)for replying, plz consider me as a beginner in the Digital Electronics world.


Bmcculla: As far I un-stood from ur writing, that the MC who enables the ALE, OK, how does the MC set the ALE (on what bases, rules), when the MC decides that it should set the ALE????

 

[williB]

the mC sets the ALE when software tells it to do a read or write to the outside world..
btw , that is also how the PC does a read or write on the ISA bus..

 

[athlon11]

MC

Thank u williB, now we know its the software who tells the MC to do the operation.

Thank u williB, now we know its the software who tells the MC to do the operation.

I have on this system a group of memory (RAM 32K*8, EPROM 32K*8, E2PROM8K*8).
In the data memory range (0000H,…….,0FE00H) we have in the memory some not used spaces:
77FFH …..8000H = Can not be used . why this range, was not clear to me.

In the documentation written : the apparent memory conflict between E2PROM and RAM sharing the same address range (0000H….77FFH) is avoided by using the /PSEN signal for address decoding. What conflict, I look at the memory figures the RAM range b/n (0000H….77FFH), and the E2PROM range b/n (8000H…9FFFH).

hope what I wrote is clear.

 

[bmcculla]

The 8051 has a couple of different memory spaces. The 2 memory spaces we are talking about are External Data (xdata)and External Program (code) memory. The 8051 has instructions to read and write to xdata (MOVX). When the MOVX intruction is executed the special bus hardware does a read or write on the memory. The hardware handles ALE, PSEN, WR, RD, etc. in order to execute the MOVX instruction.

77FFH …..8000H = Can not be used . why this range, was not clear to me.

This is probably because there is some internal memory inside the controller that uses this memory space. This memory is still considered part of xdata even though it is inside the controller because it uses the same bus.

/PSEN is the signal that lets you access xdata and code with the same bus. I think the full name is Program Storage Enable. So when when /PSEN is low the acces goes to program memory and when it is high it goes to xdata.

 

[athlon11]

bmcculla, thank u for helping.

still to be continued.