Garbage In, Garbage Out
If you let LTSpice do the work, instead of circumventing its built-in "artificial intelligence", then you will see that the circuit you drew has a stability problem. If had read the Help File, you would have learned that it is a bad idea to force an outcome by using the "uic" directive, because that usually causes un-natural results.
It is better to let LTSpice do an initial conditions solution, either explicitly as a .OP solution, or implicitly as part of a .TRAN solution. .uic specifically screws with that...
Here is the .OP solution. I purposely unbalanced the R1 R2 voltage divider +-1% to show the effect. Note that the opamp really does create a buffered "rail splitter". I labelled the nodes so we can see what is what. Read the Help File about what the .OP sim actually does.
Now, do a .TRAN sim to see what happens in the time domain as the circuit is "released" from the values found in the .OP run, above. Note that the circuit breaks into oscillation because of the attributes of the OP07 (primarily GBW). You can see the behavior after only a few us; you where simulating for thousands of cycles of the oscillation. No wonder it took lots of cpu cycles before finishing the sim. Mine runs in less than 1s.
So, how do you stabilize it? Without doing a detailed analysis, I fall back on experience. Adding bypass cap(s) to either or both rails, which you would see in a "real" application of this circuit does it: