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Logic Gates Confusion

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LOL How very disappointing !! :D


Ticket sales for that would have been enormous, especially in Cardiff !!
 
*sigh* I tried to install Logic Gate Simulator on Wine, but I get a bad exe format error. How very annoying. Logisim doesn't do timing (or it didn't when I used it ages ago.)
 
Did you download from my link or from another site ? I tried to download from another site that came up with errors, but this link seems OK

Don't think it does time, a bit primitive really, but then that suits me cos so am I !!

S
 
Nowadays people seems to learn things from videos or simulations online. I was able to undesrtand most of the basics with the help of:

Ronald Zacks - Programming the Z80.
Dom Lancaster - TTL Cookbook.

A simple breadboard (still in use after some 25 ++years) with TTL parts (yes, TTL!) complemented the process.

My first CMOS logic was tested with a simple needle multimeter.

Do not worry; that is me. Go ahead and ignore me.
 
If you can read the timing diagram, as with anything including software, all you need to know is; Input>Process>outputs. In fact if you can learn how to program PIC's , once you get past the learning curve from working designs, you will find the vast possibilities of doing much more.
PIC programmers are very cheap (almost free)

The schematic is not necessary to comprehend. In the end, it's based on a Karnaugh Map or Truth Table simplification for a Finite State Machine. Where the logic rules define what gates are needed to go from one memory state to the next. ( Each FF is a volatile memory cell or "register")

There is a simple method, (which may not be simple to learn, but simple to apply once learned) that can take any State of registers and go to the next state based on 1 or many inputs, such as the 4 bit registers, the direction bit, the clock edge and the reset input. Karnaugh Map FSM reduction method. This started many moons ago before I learnt it in '71 . It's almost looks like Sudoku but rather a simplified approach to logic problem solving. The inputs are around the table and the contents define the outputs. The methods determine which gates are needed to create the process between inputs and outputs.
 
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I dont want to confuse you even further, however have a look at the datasheet for a 4026, if you can settle for counting up only it contains the counter and the display decoder in one chip.
 
Morning Guys

I think it's time I brought this thread to a natural conclusion but before I do I need to make a few most important points.

My purpose in trying to investigate the 74LS192 was really twofold - firstly it is composite in a timer scheme I'm going to build some time in the future but secondly, and more important at the moment, it is constructed with a large number of logic gates which is a big hole in my understanding and I thought that an analysis of the contents compared to the outcome of an input to the chip would help with that.
However, I can now see that is an enormous bite of a very large cherry and would only serve to deepen my confusion.

Enter the ETO !! I've been overwhelmed by the response on here to my post. Clear explanations, excellent graphics, sources for reading and lots of damned good advice of where to look, when to look and how to go about looking. As a result I have a good method for exploring, a good place to explore and a good source of explanation to understand what I find. I've found a Logic Gates Simulator which is helping a lot and I'm now spending some time exploring and learning a lot.

As I said, it's time to put this thread to bed but not before I register a huge THANK YOU to all of you for your help. The kindness and effort of you people never ceases to amaze me and it is essential to me that you understand how grateful I am.

As for the outcome of my exploration - Watch This space !!

S
 
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