LM2596 and VCEO ?

[arvinfx]

Hi,
How much is VCEO in LM2596D ?
I asked it because I see 23.5V spikes when the switch goes off! my input voltage is 12.5 and out is 5 .
I mention it on this picture:

 

[arvinfx]

When dealing with fast edges and speed proto method affects behavior.

Manhatten style helps in some situations :

https://www.electro-tech-online.com/threads/interesting-prototype-building.163952/#post-1427629

It can introduce more parasitic C so take that into consideration. But great for
grounding.....


Regards, Dana.

I saw this method before look like easy. But in my prototype all high frequency and high current joints are soldered.

 

[Nigel Goodwin]

I saw this method before look like easy. But in my prototype all high frequency and high current joints are soldered.

But you've got long wires, and loads of stray capacitance and inductance, I wouldn't expect it to work terribly well. Layout on something like this is pretty crucial.

 

[Diver300]

The circuit needs capacitance with the minimum series inductance, as close as possible to the LM2596.

The breadboard layout is terrible for that, and the electrolytic capacitors have significant ESR. You need some ceramic capacitors close to the LM2596

 

[danadak]

I saw this method before look like easy. But in my prototype all high frequency and high current joints are soldered.

Those are soldered joints. The large PCB serves as a ground plane, then small islands of
one sided PCB placed, sticky side down, to create a connection areas for soldering. So
although I stated it introduces C its relatively small, just a small amount by connection
island sandwich, eg. ground plane | fr4 insulator of one sided PCB | top of the island.
At RF freqs the C is impactful, but at SMPS clock rates not so much.

Ground is outstanding in this approach.

Capaitor ESR matters a lot, various technologies produce various results for same level; of C :

OSCON is polymer tantalum, best in class for bulk caps.


Regards, Dana.

 

[Ian Rogers]

Just a note!!! When I made my first power supply, the "pre" filter was a tad out I used a 80mH inductor and a 1uf cap ( should have been 100uf ) and mine blew up... Didn't know much back then...

 

[Tony Stewart]

Pls see last picture of post No.17

ok but with long ground wires adding ground shift with 10nH/cm try across to output cap and use braid or litz wire or desolder gauze for gnd wires.

 

[arvinfx]

Just a note!!! When I made my first power supply, the "pre" filter was a tad out I used a 80mH inductor and a 1uf cap ( should have been 100uf ) and mine blew up... Didn't know much back then...

once I blew up a 34063 due to high current request in output. almost near to lost my eyesight!

 

[arvinfx]

Guys, Thanks. I will finish the project and release the result in here your idea really helped me .

 

[Nigel Goodwin]

once I blew up a 34063 due to high current request in output. almost near to lost my eyesight!

A good reason for wearing glasses

An ex-work colleague of mine (who didn't wear glasses) had to go to A&E with a solder splash on his eye ball!

Even worse, at A&E they simply scraped his eyeball with a scalpel - I hope they had steady hands?.

 

[Tony Stewart]

Pls see last picture of post No.17

Yes I see large current loops with 10 nH/cm added to your schematic for every jumper and BB ground strip and mutual coupling everywhere resulting in a flyback pulse around 1 cycle at 20 MHz. This is where 2 pF diff. Probes are needed to remove measurement error from inductive ground and probe capacitance.

These spikes are well beyond the servo BW of the regulator yet V=I*ESR+LdI/dt results in spikes . Try to estimate reasons for signals, using what you know.

If you do not have diff probes, use a series cap+50Rs to SMA 50 ohm coax to 50 ohm terminated DSO using same small <2cm loop , you can capture better results with 50% atten.

The value of a ground plane is a low impedance from low geometric ratios of gap height, H to conductor width, W for high current slew rates

for e.g. H/W= 12 ratio on FR4 determines Zo=150 ohms or H/W=1, Zo < 70 ohms
for Height of FR4 dielectric, H[mm] and track width, W[mm]
in your case with air dielectric and a huge gap for H/L ratio, your Zo is very high > 300 ohms resulting in a mismatch >= 10 MHz.

To use a breadboard, all highspeed signals need twisted magnet wire with orthogonal wiring on inductive high-speed H fields and core to minimize coupling.

 

[Tony Stewart]

To use a breadboard, all highspeed signals need twisted magnet wire with orthogonal wiring on inductive high-speed H fields and core to minimize coupling.

The same was with a WW back plane with 20 PCB's using TTL in the late 70's . I inherited that design built with aerospace wiring in bundles that had to be ripped out and re-wrapped with random point to point logic wiring and twisted magnet wire pairs for all the analog signals used for eddy current PLL to get 80 dB SNR. The important part was to prevent the noise from exceeding the CM range where the OA diff gain drops to near 0 dB While the CMRR also drops to 0dB.

The magnet wire pair capacitance shunted the stray logic >20 MHz noise stray pF One race condition in logic, was treated with a LPF shunt cap to get all working in this custom SCADA robotic network.

 

[arvinfx]

I almost finished the project.

This is the result:

Now the peak spike is 18.5V . It is much better. I am suspected to diode speed reaction . diode is 1N5844