IR2106 hi/lo FET driver. Understanding the datasheet.

The functional circuit, as per the datasheet, is this :-

I'm puzzled as to the exact operation of the highlighted section, which seems to show the Hi driver's pulse generator controlling the Lo driver's output via the NOR gate, despite the introductory text saying :-


I could understand a desire to force the LO output low when the HO output is high, to prevent cross-conduction, but the table says that no cross-conduction prevention logic is present.
I also wonder if the NOR gate should really be a NAND gate, in order to force LO low (not high) when the under-voltage detection logic senses too low a Vcc voltage.
Any thoughts?

It's not. You have your signal directions reversed. The signal direction goes from the undervoltage detector and splits up to go to both the NOR gate and the pulse generator.

alec_t said:

I also wonder if the NOR gate should really be a NAND gate, in order to force LO low (not high) when the under-voltage detection logic senses too low a Vcc voltage.

Click to expand...

NOR is correct.
What the under-voltage signal goes high, the circuit output also goes high, causing the bridge output it is connected to to go low.
Notice that the high-side under-voltage signal does the same thing.

Ah, that makes sense. Thanks guys.