RonDumas
New Member
With a 16f876 running a 4Mh external osc. I would like to use the Tmr0 overflow interrupt to trigger a data transmit to the usart.
Could someone better explain the calculations to determin the timing.
For instance, I believe the timer will overflow every 255 clock cycles.
If I use the 1:8 TMRO rate does this mean 255 * 8 = 2040 cycles?
Or are these numbers to be divided by 4 ? Multiplied by 4 ?
I'm using the internal osc to drive Tmr0.
What is the difference between clock cycles and instruction cycles?
Is it one instruction cycle to every 4 clock cycles?
Am I way off base?
Could someone better explain the calculations to determin the timing.
For instance, I believe the timer will overflow every 255 clock cycles.
If I use the 1:8 TMRO rate does this mean 255 * 8 = 2040 cycles?
Or are these numbers to be divided by 4 ? Multiplied by 4 ?
I'm using the internal osc to drive Tmr0.
What is the difference between clock cycles and instruction cycles?
Is it one instruction cycle to every 4 clock cycles?
Am I way off base?