Interrupt inMicrocontroller

[Nagarathna]

Hi,

I would like to know what happens when an external interrupt occurs from the hardware point of view.
How does the cpu come to know an interrupt has occured which it has to process.

 

[misterT]

In AVR microcontrollers:

- Global interrupt flag and interrupt specific flag are set.
- Program counter is automatically pushed into stack and new value is loaded to point to interrupt vector location (program execution jumps to interrupt handler routine).

.. Or are you interested how the hardware interrupt handler is implemented in hardware level? Only the engineers who designed the chip know for sure. Block diagrams usually show no more details than the interrupt handler connecting to an internal databus.

 

[Jon Wilder]

When an interrupt is triggered it tells the program counter to jump to a specific address location in program ROM, known as the "interrupt vector" address. In PIC microcontrollers, this address location is 0x04.

The idea here is to have the first instruction of the ISR reside at this address, which you can do with "org" directives. Or you can have a jump instruction (i.e. "goto ISR") reside at that address that will jump the program counter to the ISR code segment once the interrupt tells the PC to jump to the interrupt vector address.

 

[Nagarathna]

Hi,

Thanks for all the reply,is their any connection between interrupt and PCA ?
If my cpu or processor is doing a mathematical operation in background how will it sense an interrupt,will it be polling a register and performing the mathematical operation simultaneously ?

i want it a little brief this was an interview question.

 

[Jon Wilder]

An interrupt is exactly as its name implies. The processor runs the main code under normal operation. Once an interrupt is triggered, it "interrupts" the main program code to carry out another task.

Each instruction in a program resides at an address location in program ROM. Under normal operation, the program counter jumps to each program ROM address location sequentially, executing each instruction that exists at each program ROM address location.

Upon triggering of an interrupt, the program counter jumps to the "interrupt vector" address location in program ROM and carries out whatever instruction that exists at that address location. The idea is to have a jump instruction reside at the interrupt vector address location that will then jump the program counter to the start of the interrupt code. At the end of the interrupt code you have a "return from interrupt" instruction that jumps the program counter back to the "pre-interrupt" address location to resume running the main code.

This means that if in the main code you're running a math operation and an interrupt condition exists, the processor will stop what it's doing to execute the interrupt code segment, known as the "interrupt handler". If you're using multiple interrupts, then you write the interrupt code to poll each interrupt flag bit to determine what set the interrupt, then have it jump to the appropriate code segment that the processor is to execute for each interrupt.

It doesn't get much simpler than this. Perhaps it would help if you could tell us exactly which processor you're referring to.

 

[misterT]

If my cpu or processor is doing a mathematical operation in background how will it sense an interrupt,will it be polling a register and performing the mathematical operation simultaneously ?

If the mathematical operation is "atomic" then the operation will be finished before executing the interrupt. Single clock cycle operations are atomic.

 

[Nagarathna]

Hi,

Fine ,nice,thanku,but if somebody ask me to explain interrupt in terms of PCI ,what will the explanation be ?

 

[misterT]

if somebody ask me to explain interrupt in terms of PCI ,what will the explanation be ?

Plug-and-Play-HOWTO: PCI Interrupts

 

[Jon Wilder]

Ah you're speaking of interrupts and how they pertain to computers. The title threw us off a bit as we thought you were speaking of strictly microcontrollers, not full blown PCs.