Please help me explain with the highlighted part.Even though there is no voltage drop across RG, it still conveys a voltage to the transistor's gate. If you remove RG, then the gate is floating.
So why not make RG zero ohms? That will also convey the voltage to the gate. However, it will create a low impedance for a signal that is applied to the gate, which will then just be RD ohms away from an AC ground at VDD.
We need a resistor to help maintain whatever input impedance is necessary at the gate.
If you look at the DC picture, it goes something like this. Initially, no current flows through the transistor and so the drain is at VDD. If the drain is at VDD, that means that the gate is also at VDD. But if that's the case, the transistor is actually turned on and so current flows, causing a voltage drop on RD. But, aha, we have feedback! If current flows through RD, then the drain is not in fact at VDD and therefore neither is the gate, so the transistor is not quite as turned on as we thought. The solution to this feedback loop is the operating point, and as you can see, RG is very much involved in it.
What ?? How can it be infinite anymore ? Please do small-signal analysis for this circuitIf RG = 0 then Vin will directly connect to drain of transistor but the input current still has to be zero, IG = 0 not ID .
So the input impedance isnot RD .
One of the limitation factor is a input signal resistance. Because if Rs is very close to Rg the voltage gain will drop to Av = Rg/Rs.I think we want Zin as large as possible, if so we can choose RG very large. Is the a limited range for RG?
I spot a error in your equation. Zin is positive not negative.
[LATEX]Z_{in} = \frac{ V_{in} }{ I_{in} } = \frac{ R_{D}+ R_{G}}{1 + g_{m}. R_{D}}[/LATEX]
Thanks, I didn't pay attention to the direction of input current, Iin.I spot a error in your equation. Zin is positive not negative.
What is the significance of this evaluation? From the formula, it says that the input impedance will be a constant if load resistance, Rd is much smaller than RG.And if Rd<<RG
[LATEX]Z_{in} = \frac{ V_{in} }{ I_{in} } \approx \frac{R_{G}}{1 + g_{m}. R_{D}}[/LATEX]
Yes, I see it. My mistake was to consider Iin = Ig = 0. That is not true.Another 'quick' view is that with the drain connected directly to the gate, with the right constraints on the input (if we had one) the circuit then looks like a resistor RD in series with a current source M1 in series with RS. So in any input to the gate now (with the proper constrains in place) sees an impedance equal to simply RD. So Zin=RD.
I am not sure what you meant by input constraint. Is it input impedance or input voltage?Of course maintaining the input constraint would probably not be possible. But for inputs close to that requirement the input Z would look nearly equal to RD alone.
If you mean input impedance, do you mean that input impedance has to be a constant and the only thing we can do is to choose RD as small as possible but not zero?The constraint on the input would be that it has to be a voltage nearly equal to the self biased gate voltage when the gate is shorted to the drain. Again, this probably isnt easy to get, but it does show that the impedance is not infinite, no way, but goes very low as RD will normally be much lower than say 1 Megohm.
Hmm, after this simplification the equation looks exactly the same as a "Miller" equation.[LATEX]Z_{in} = \frac{ V_{in} }{ I_{in} } \approx \frac{R_{G}}{1 + g_{m}. R_{D}}[/LATEX]
What is the significance of this evaluation? From the formula, it says that the input impedance will be a constant if load resistance, Rd is much smaller than RG.
We want Zin to be a constant, right? If so, the condition for load resistance is Rd << RG is a must.
Hi,
I meant that the input voltage would have to be held constant.
But if we just look at it as a variable current source with variable input voltage, then we see that we have the highest end impedance equal to Rd at the output, and the lowest equal to Rs (ideal device) in parallel with Rd. So we have those two extremes at the output, Rd and Rs, where Rd is the highest we can have and Rp equal to Rs in parallel with Rd as the lowest at the output. So the output looks like either Rd or Rp, and the input looks like Rg in series with either one of those. So the input impedance extremes are:
Rg+Rd
and
Rg+Rp
In other words, if the FET output is an open, we have Rg+Rd, and if the FET is a short, we have Rg+Rp as input impedance.
I think you are considering the large signal case where the input voltage swing is large enough to take the FET from to cutoff to full on (or nearly so).
At cutoff the FET certainly behaves as though it were open, but at full on bias the FET doesn't behave like a short. In the full on case, gm may become large, but the gate still has an effect on the output current. The FET only behaves like a short if it really is shorted; damaged, with the gate having lost all control.
If we calculate the small signal input impedance and let gm -> infinity, the impedance reaches a limiting value of Rg + Rs||Rd - (Rg*Rd)/(Rs + Rd). This is equal to your Rg +Rp value with a correction term shown in red.
Hi there Electrician,
That's an interesting reply, but i am afraid i do not follow your logic here. Im sure it is just a matter of a few more words to clear this up though.
What i see so far is that in your equation for Zin, we have:
Zin=Rg+(Rs*Rd/(Rs+Rd))-(Rg*Rd)/(Rs+Rd)
and the negative part is the part you had shown (nicely) in red.
Simplifying Zin we get:
Zin=Rs*(Rg+Rd)/(Rs+Rd)
Using values (note a high Rg as typical) of:
Rg=1000000
Rd=1000
Rs=100
We get:
Zin=Rin=91000 Ohms
gm Zin
.001 524333
.01 166833
.1 99198
1.0 91826
10 91083
This is lower than Rg by a factor of at least 10.
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