Module mcu (clk, rst, en, p_in, p_out, t_in, t_out, i_in,i_out, rx_in, tx_out ,a0,a1,a2,d0,d1,d2,d3,d4,d5,d6,d7,a,b,s0,s1,s2,f,........etc);
//Input, output declaration
Rst= reset input
Clk= clock input
En= enable input
Port
P_in=port input
P_out= port output
Timer
T_in = timer input
T_out = timer output
Interrupt
i_in= input for interrupt
i_out,= output for interrupt
ram
wr
wd
ram
read
write
enable
//Interconnect signals
wire alu [3:0]
wire decoder [7:0]
reg counter [3:0]
// add alu
Mcu_alu (a,b,s0,s1,s2 f);
Input a,b,s0,s1,s2;
Output f;
Reg [3:0];
Always @(s0,s1,s2);
Begian
Case (s0,s1,s2);
3b’000 :f=(a&b);
3b’001:f= (a|b);
3b’010 :f= ~(a&b);
3b’011 :f= ~ (a|b);
3b’100:f=(a^b);
3b’101: f=(a*b);
3b’110: f=(a+b);
3b’111:f=(a-b );
End case;
//Add decoder
Mcu_decoder (a2,a1,a0, d7,d6,d5,d4,d3,d2,d1,d0);
Input a2,a1,a0;
Output d7,d6,d5,d4,d3,d2,d1,d0;
Wire [7:0];
Always @(a2,a1,a0);
Begin
Case (a2,a1,a0);
4’b000:( d7,d6,d5,d4,d3,d2,d1,d0)=00000001;
4’001: (d7,d6,d5,d4,d3,d2,d1,d0)=00000010;
4’b010: (d7,d6,d5,d4,d3,d2,d1,d0)=00000100;
4’b011: (d7,d6,d5,d4,d3,d2,d1,d0)=00001000;
4’b100:( d7,d6,d5,d4,d3,d2,d1,d0)=00010000;
4’b101:( d7,d6,d5,d4,d3,d2,d1,d0)=00100000;
4’b110: (d7,d6,d5,d4,d3,d2,d1,d0)=01000000;
4’b111: (d7,d6,d5,d4,d3,d2,d1,d0)=10000000;
Endcase
//add counter
module up_counter(current state, next state ,clk)
input current state ;
input clk;
output next state;
reg 3:0
always @ (posedge clk);
begin
next state <= current state +1 ;
end
endmodule
Endmodule