Info on on VHDL & Verilog simulation

Hi All,

I have been direct to this site. I have a FYP needs to design a logic simulator, I select this only project is that I have EE background and programming knowledges.

My professor only gives me some keywords as:
Hardware Description Language, WDL and Event Driven Simulation.

I have checked all from the web but don't know how a logic simulator could be built by those keywords. As parts of project, should I build the praser/compiler and waveform generator too.

Can somebody help to advise if this forum or other forums right to discuss about.

Tks/Brgd.

One of the programs we're using here is the Xilinx Integrated Software Environment (ISE). Its a fully integrated package that provides the HDL environment, emulation & timing analysis, device programming, plus a few other features I haven't tried. As far as I know, we've used it for ABEL and VERILOG, but I'm really not an expert on it so that's about all I can say.