I2C with several masters

electroRF · Oct 31, 2013

Hi,

I'd like to design a system where several Masters working with one slave.

Each Master will have different priority, so that if the master with the higher priority would like to transmit data to the slave, it'd be able to release the bus from the current active Master (which has lower priority), and start its own transmission.

How would you design such system?

The communication interface must use only 2 lines - SDA and SCL (I can't add more lines).

Thank you.

geko · Oct 31, 2013

I don't believe the I2C protocol supports the ability to allow one master to interrupt another so you can't do it, at least not within the specification of I2C

Since control of the I2C-bus is decided solely on the address and data sent by competing
masters, there is no central master, nor any order of priority on the bus.

See section 3.1.8
**broken link removed**

ikalogic · Oct 31, 2013

Hmm.... what you want to do is absolutely possible, but it would not be called I2C.

As a matter of fact, CAN bus work exactly like that.. maybe you can start by reading about how CAN bus manages multiple maters (which it does), then you can implement this with the two lines used by the I2C..

If i was you, i would re-implement something similar to the CAN bus with only 1 wire (the SDA). Of course, this would not be called I2C anymore, and you wouldn't be able to use the I2C hardware of your micro controller, you would have to "bit bang" your own protocol.

If you don't need to go too fast (and depending on your programming skills and the time you have), it is doable!

misterT · Oct 31, 2013

There are lots of projects and discussion about Multi-Master I2C. Even the I2C-bus.org addresses this topic https://www.i2c-bus.org/MultiMaster/
I don't know how common it is to have many masters, but it is not considered to be against the I2C specs. They even spec two types of masters.. (single)master and a multi-master.

If you google "i2c multi master" you will get lots of hits. I have never build that kind of system, so I can't help with details. Study the existing projects and the **broken link removed**. I hope they give you ideas to build your system.

dougy83 · Oct 31, 2013

While it doesn't seem that it's normal to signal a cancellation of transaction, there could be a few ways to manage it.

You could signal a transaction cancellation request by stretching the clock signal - a transmitting master could detect this stretch and cut the transaction short gracefully (if appropriate at that time).
If the transactions are small, it would be easier to just wait for the transaction to complete, then the next master could claim the bus.

What is the slave device and how large are the transactions?

electroRF · Nov 1, 2013

Hi mates,
Thank you very much for your feedbacks!

I decided to go for this project because my friend who was in a job interview got this question:
"implement a protocol of Multi-Master on 2-lines bus (as continuance to I2C) - you got n Masters with 1-to-n priority and they all can access the bus simultaneously".

I'd like to design such protocol but I'm not sure how to start.

misterT · Nov 1, 2013

Start by reading existing protocols:
http://ww1.microchip.com/downloads/en/AppNotes/00578b.pdf
http://documentation.renesas.com/doc/products/mpumcu/apn/rej06b0634_h8sap.pdf

electroRF · Nov 1, 2013

Hi T,
Thank you!

I read the excellent microchip AppNote that you shared.

That is even though i'm well versed in I2C and I already have a PIC18F (I2C Master) -- EEPROM (I2C Slave) --- GLCD (I2C Slave) here which I work on.

I'm trying to figure out how should I change the protocol in order for it to fit to the requirement of having 1-to-n priority Masters, so that the Master with the higher priority will be able to interrupt the lower priority masters.

ikalogic · Nov 1, 2013

electroRF said:
I'm trying to figure out how should I change the protocol in order for it to fit to the requirement of having 1-to-n priority Masters, so that the Master with the higher priority will be able to interrupt the lower priority masters.

Generally, this is done in 3 steps:

1- you have to make sure all devices are perfectly synced
2- the lower priority address (for a message) is 0xFF, and the highest is 0x00, simply because if both are written in the same time on the bus, the 0x00 will overwrite the 0xFF. This is also true for all addresses in between
3- each master have to continuously check if it still have control of the bus. This can be done by making sure that what it is sending is actually being written on the bus. For instance, if a master is writing 0xFF, and another is writing 0xF0, after the first 4 bits (0xF) one of the two master will fail to write the next bit, so it should go idle or retry later or whatever..

Hope this helps.

electroRF · Nov 1, 2013

Hi IKA
Thank you very much for these guidelines, they are very helpful

So the new protocoal would be as follows:

Say that n masters see that SDA=1, SCL=1, i.e. the bus is idle, and they all try to get control of the line.

(is that how a master decides the the bus is free? by sensing whether both SDA and SCL are high?
If so, for how long does it keep sampling the lines to see they're still HIGH before deciding the bus is free? )

Before they attempt for a Start bit, each Master (that wants to take control of the line) needs to send:

1st highest priority master sends - 0x00 - 0000-0000
2nd highest priority master sends - 0x01 - 0000-0001
3rd highest priority master sends - 0x20 - 0000-0011
4th highest priority master sends - 0x40 - 0000-0111
...
8th highest priority master sends - 0x80 - 0111-1111
and so on.

At each bit's transmission, the master should check the if the value of the SDA is the value of the bit it transmitted.

And only then, the Master with the higher priority will be able to send the START BIT.

Is that what you meant?

1- you have to make sure all devices are perfectly synced

In Multi-Master mode, must they all use the same clock frequency?

It doesn't state that in spec that in multi master mode they must have same clock frequency.

ikalogic · Nov 1, 2013

electroRF said:
Hi IKA
Thank you very much for these guidelines, they are very helpful

So the new protocoal would be as follows:

Say that n masters see that SDA=1, SCL=1, i.e. the bus is idle, and they all try to get control of the line.

(is that how a master decides the the bus is free? by sensing whether both SDA and SCL are high?
If so, for how long does it keep sampling the lines to see they're still HIGH before deciding the bus is free? )

Before they attempt for a Start bit, each Master (that wants to take control of the line) needs to send:

1st highest priority master sends - 0x00 - 0000-0000
2nd highest priority master sends - 0x01 - 0000-0001
3rd highest priority master sends - 0x20 - 0000-0011
4th highest priority master sends - 0x40 - 0000-0111
...
8th highest priority master sends - 0x80 - 0111-1111
and so on.

At each bit's transmission, the master should check the if the value of the SDA is the value of the bit it transmitted.

And only then, the Master with the higher priority will be able to send the START BIT.

Is that what you meant?

Yes.. that's it

electroRF said:
In Multi-Master mode, must they all use the same clock frequency?

It doesn't state that in spec that in multi master mode they must have same clock frequency.

Hmm.... maybe i am wrong about that.. Here is the point: If all master have the same clock, and those clocks are synchronized, then i am sure it would work like a charm.. I am not able to imagine (simulate in my head) what will happen if all master have clocks that are different or not aligned...

misterT · Nov 1, 2013

ikalogic said:
If all master have the same clock, and those clocks are synchronized, then i am sure it would work like a charm..

The first one to send "start" condition would control the clock and others would sync to that. If some higher priority master wants to interrupt, then it does that..

ikalogic · Nov 1, 2013

Honnestly, i don't think I2C is quite adapted to multi master system.

If i had to do it, and if all i had was the 2 SDA / SCL lines, i would get rid of the SCL, and re implement a simpler, fixed baud rate, UART like protocol on the SDA line... but that's only my humble opinion

electroRF · Nov 1, 2013

hi T and IKA,
Thank you.

Is it correct to say that the a master will try to take control of the bus only if it senses that both SCL and SDA are HIGH?

Did you happen to see how long does it sample the 2 wires to see that they're still HIGH, before it takes control?

Regarding the Clock Frequency,

It reads in the Spec that masters can have different LOW / HIGH Period, and therefore the SCL's LOW period is set by the longest LOW Period of all masters, and the SCL's HIGH period is set by the shortest HIGH Period of all masters.

that is called Clock Sync.

So it seems they can work together while having different frequencies, that is until arbitration takes place, doesn't it?

ikalogic · Nov 1, 2013

electroRF said:
hi T and IKA,
Thank you.

Is it correct to say that the a master will try to take control of the bus only if it senses that both SCL and SDA are HIGH?

well, that's one way of doing things, at least, that's the way to detect if the lines are idle.

electroRF said:
Did you happen to see how long does it sample the 2 wires to see that they're still HIGH, before it takes control?

Regarding the Clock Frequency,

It reads in the Spec that masters can have different LOW / HIGH Period, and therefore the SCL's LOW period is set by the longest LOW Period of all masters, and the SCL's HIGH period is set by the shortest HIGH Period of all masters.

that is called Clock Sync.

So it seems they can work together while having different frequencies, that is until arbitration takes place, doesn't it?

hmm.. seems like it would work as you say.

electroRF · Nov 2, 2013

Thank you IKA

I looked again at the signals diagram of the I2C, and I wonder - the NACK there means that the slave did NOT receive the data byte sent by the Master, right?

I just wonder why would the datasheet show an Error state where the slave does not get the data sent to it by the master.

ericgibbs · Nov 2, 2013

Hi RF,
The NACK is sent by the Master to to tell the Slave to Stop transmitting, its not for errors.

look at this pdf. Pages 17 & 18
Eric

electroRF · Nov 2, 2013

Hi Eric,
Thank you for your comment.

I disagree with you,

this diagram is for Master's TRANSMISSION MODE - i.e. the Master is the one who sends bytes and the Slave receieves.

Therefore it is the slave who sends this NACK, isn't it?

geko · Nov 2, 2013

ericgibbs said:
Hi RF,
The NACK is sent by the Master to to tell the Slave to Stop transmitting, its not for errors.

look at this pdf. Pages 17 & 18
Eric

I am also a little confused by the Microchip timing diagram that RF posted since it is showing the R/W bit low ( write). This would indicate the master is writing the data to the slave so you would expect the slave to ACK the transfer under normal operation as shown in the document you linked to?

ericgibbs · Nov 2, 2013

hi RF,

The Not part of the NACK only indicates its 'sense' [remains high] not that an error has been detected.
This occurs at the 9th clock pulse.
As the PDF states, the meaning of these acknowledgements will depend on which bytes are being transferred and what device is being talked too.

EDIT:
Extract:
This is the purpose of the I2C NACK bit that concludes a transfer from the slave IC to the master device. If the master ACKs the last byte and then attempts a STOP condition, the slave might put a 0 on the data line that blocks the STOP condition. If the master NACKs the last byte then the slave IC gives up and everybody exits cleanly.

I2C with several masters

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