Hi Friends,
Suppose there is a microcontroller with I2C module and an I2C EEPROM and they are interfaced.
Is static timing analysis required for the analysis? By static timing analysis , i mean the constraints for setup time and hold time.
For start and start condition , at what time will the master make the SDA line low with respect to the Clock rising or falling edge? What parameter should i look at?
For eg;- when the master first issues a start condition (SDA turning low when clock is high) , there should be a minimum start hold time (for the slave) only after which clock turns low. At what time will the master pull this SDA line low with respect to the clock's falling edge..
Thanks in advance.
Suppose there is a microcontroller with I2C module and an I2C EEPROM and they are interfaced.
Is static timing analysis required for the analysis? By static timing analysis , i mean the constraints for setup time and hold time.
For start and start condition , at what time will the master make the SDA line low with respect to the Clock rising or falling edge? What parameter should i look at?
For eg;- when the master first issues a start condition (SDA turning low when clock is high) , there should be a minimum start hold time (for the slave) only after which clock turns low. At what time will the master pull this SDA line low with respect to the clock's falling edge..
Thanks in advance.