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How to switch a large-V load with a P-channel mosfet and small-V unipolar clock?

Thread starter #1
i can switch the supply voltage with a unipolar clock, if the clock has the same peak V as the source supply



The phases are as desired. I want the P mosfet to turn on when clock goes low.

Problem is: if i make the source V higher than the gate V, i get a flat line output.



How to switch a high-V load with a low-V clock, on a P-channel mosfet?

Need to be able to vary the large V on the P-channel mosfet, and switch should still work without changing any component values. Eg, the load-V may be 6V, or 20V, and circuit should still switch with same components.

Assume unipolar power supply for both transistors. Assume switching freq's from 20 kHz to 80 kHz. But the switching freq will never change, so it's ok if component values assume a fixed freq. Should also work if clock high is 3.5V, but clock high-V will never change, so it's ok if component values assume a fixed clock V.

Specific component values would be nice, but not necessary. Mainly just need the circuit. I can solve component values later.

Prefer to make this a single-stage if possible, or just 1 driver stage if possible.

Thx
 
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#2
The driver needs to be two stage; an N-channel (or NPN) device that is controlled by a voltage relative to its source or emitter, in turn "pulling down" the gate of the P channel device, via and appropriate resistive divider if needed to limit the gate-source voltage on that.

This is the principle, whether you use FETs or bipolar transistors:
http://www.w9xt.com/img_1224968365_15450_1308499014_mod_380_283.jpg

If the two voltages are regulated and have a constant offset, you may be able to cheat and use a zener diode between the logic level signal and the P channel gate, with a gate-source resistor to ensure proper turn-off with a high level output.
eg. Use a 5.1V zener if the logic is 5V and the higher supply is 10V.
That's not true independence but can function in the appropriate circumstances.
 
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Thread starter #4
Fantastic answer, rjenkinsgb.

The driver needs to be two stage; an N-channel (or NPN) device that is controlled by a voltage relative to its source or emitter, in turn "pulling down" the gate of the P channel device.
When you say the driver is 2 stage, you mean the whole system is? There's just clock, 1 driver stage, and 1 mosfet stage.

In that circuit:
R1: limits current going to Q1?
R4: DC bias? Why needed? Won't that lower the base V? Wait, no-- it makes the transistor operate in linear region?
R3 and R2:
- limit current passing through Q1?
- passes 10V thru Q1. Wait-- so Q1 can switch 10V with a 5V base, but Q2 can't? Cuz Q1 is linear amplifier instead of switch? If that works for Q1, why not make the mosfet operate in linear region, and eliminate Q1?
- form a resistor divider on Q2 gate? Why needed? Don't we want Q2 gate to get full scale 10V?
D1: siphons off backwash from inductive loads?
Can all stages share same ground?

If the two voltages are regulated and have a constant offset, you may be able to cheat and use a zener diode between the logic level signal and the P channel gate, with a gate-source resistor to ensure proper turn-off with a high level output.
eg. Use a 5.1V zener if the logic is 5V and the higher supply is 10V.That's not true independence but can function in the appropriate circumstances.
Thx for the cheat! I don't care about Independence, as long as it switches :)

Ok, if the mosfet power supply we're to vary, then what part of your cheat would need to vary along with it?

Thx!
 
#5
In that example circuit:

Remember that the base-emitter junction of a bipolar transistor is effectively a diode and conducts at around 0.7V regardless of current through it.

There must be a series resistor to limit the current, otherwise either the transistor or whatever feeds it will be overloaded or destroyed.

The base-emitter resistors ensure a full turn-off even if there is slight leakage in other components and also speed up the turn-off time, increasing efficiency in a switching circuit.

The second transistor is effectively being controlled by a switch to ground (the first transistor). The two stages are similar but mirrored between positive and negative supplies. (eg. the first stage is operated by a signal switching to a positive voltage).


As long as the base current x device current gain is greater than it's collector current, a transistor will operate in saturated switching mode.
eg. R1 & R4 10K, R2 & R3 1K should be fine for a moderate load up to possibly 100mA with typical medium-gain transistors.
(Due to the base diode effect, the voltage division is not equal despite equal resistor values).

Using FETs with your 10V upper supply, you could omit the series resistors (as FETs are voltage driven rather than current driven) and just have gate to source resistors on each transistor - again, to ensure proper turn-off with no gate-source voltage when not actively being driven.


The "zener cheat" will only work reliably if the two voltages are kept fairly stable. With a varying high voltage you need some form of two-stage drive, or use a mechanical or opto relay.


Edit - reading your points again; a transistor / FET is controlled by a current or voltage on the base or gate relative to its own emitter or source;
With a single transistor as in your original circuit, there is no way of setting that voltage to zero - the signal is varying between 5 - 10V negative of the transistor source so it never turns off.
 
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Thread starter #7
you may be able to cheat and use a zener diode between the logic level signal and the P channel gate, with a gate-source resistor to ensure proper turn-off with a high level output. eg. Use a 5.1V zener if the logic is 5V and the higher supply is 10V.
So, if the higher supply is 20V, and logic V remains 5V, then zener needs to be about 10V?
 
Thread starter #10


Seems to give opposite the normal P behavior, which should be:
  • clock low -> Q2 gate low = Q2 closed
  • clock high -> Q2 gate high = Q2 open
This is opposite, no?
  1. On clock low -> Q1 base low.
  2. On Q1 base low, Q1 open.
  3. On Q1 open -> Q2 gate is seeing V+ (through R3.).
  4. On Q2 gate = V+ -> Q2 open
  5. Therefor, on clock low-> Q2 open. Not expected P-channel behavior.

  1. On clock high -> Q1 base high.
  2. On Q1 base high, Q1 closed.
  3. On Q1 closed -> Q2 gate is seeing ground (through R2 and Q1.).
  4. On Q2 gate = ground -> Q2 closed
  5. Therefor, on clock high -> Q2 closed. Not expected P-channel behavior.
 
#11
The expected behavior of a PNP (or P-channel mosfets) conducts when you pull the base (or gate) Low.

More specifically, when the gate is some volts below the source in a mosfet, or current can flow OUT of the base of a PNP.

So when you say, closed, you mean current is flowing through the device. So when clock is high...

Current flows through Q1 (and therefore the voltage from emitter to collector is about 0.1v. Then, current can flow from the base of Q2 which means current is also flowing in Q2 when clock is high.
 
Thread starter #12
Yes, by "closed" I mean the switch is closed, or on.

When clock is high, p channel mosfet should be open/off, right?

With a unipolar power supply, are the 2 states of the P-channel mosfet 0V and Vss? Or 0v and -Vss?

THX
 
#13
Q1 is logically an inverter; when the input to that is high, the output is low and vice-versa.

Q2 (or a P-channel FET in that position) is working normally - and acting as another logical inverter - but itself fed with an inverted signal from Q1.

The two cascaded inversions mean the final output is in phase with the overall circuit input rather than having a single inversion as with the P-channel device within a single-supply circuit as your very first example.


Edit - if you do not want the double inversion, you can reconfigure Q1 to common base.
For that, connect the base directly to +5V and connect the emitter to the logic signal via eg. a 1K resistor.
Or use a FET with gate to +5V and source to the logic signal.

You still need the base resistors on Q2.

In that mode of operation, the transistor gives no current gain so all the current to the upper transistor base or gate is provided by the logic pin, but no current is drawn until the logic signal is low, providing base current or gate voltage to Q1.

That can only work if there is enough difference in voltage between the logic and output (Q2) supply to turn on Q2.

I can't find an appropriate logic-switch example diagram, but this shows the basic common base principle -
https://www.elprocus.com/wp-content/uploads/2017/09/2017-09-12_16-01-44.jpg

The base (or gate) is connected to a fixed voltage somewhat higher than ground, then a signal input to the emitter side is output in phase at the collector.
In your application, the 5V logic supply is the perfect base bias voltage, with the higher voltage supply (10V or more) providing the collector load supply.
 
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Thread starter #14
So I'm correct that your circuit turns on the p channel when the clock goes high? Not my intention.

My first example works as desired regarding phase. When clock goes low, I want the p channel mosfet to turn on.

The only issue was how to turn on with different supply voltages.

Should we just use a p channel driver instead of N?

Thx!
 
#15
I've not created a circuit in ltspice before, so I hope this works OK..

This is the common-base version that keeps a single inversion:


V1 is the 0-5V logic signal, V2 the 5V supply and V3 the 10V supply.
The red plot the the logic waveform and blue the output to the load.
Green is the voltage on the transistor emitter, varying between 5V and about 4.3 when the logic signal is low.

.asc file attached so you can use it in ltspice yourself.
highdriver.png highdriver.png
 

Attachments

#17
So I'm correct that your circuit turns on the p channel when the clock goes high? Not my intention.

My first example works as desired regarding phase. When clock goes low, I want the p channel mosfet to turn on.

The only issue was how to turn on with different supply voltages.

Should we just use a p channel driver instead of N?

Thx!

Yes, a P-channel driver will be a much better option. Make sure the driver works as you want (turns on he mosfe when your clock is low). Also, the driver will turn off much faster than the one in an earlier post.
 
Thread starter #18
Wow, many thx for spending time and brain, rjenkinsgb! Thx for files. I'm new to LT Spice, will take me some time to figure out (more time than you).
In your application, the 5V logic supply is the perfect base bias voltage, with the higher voltage supply (10V or more) providing the collector load supply.
Does that mean your config would not work with a different clock V, or a different mosfet supply? There's some relationship between the two V's?

I'm seeking a config that will work even if clock is a different V, eg 3.5V, or even if mosfet supply is different, say 6V, or 20V. Plz see my op for updated description.

Yes, a P-channel driver will be a much better option. the driver will turn off much faster than the one in an earlier post.
Why faster? This article says N-channel is faster.
http://www.circuitstoday.com/pmos-vs-nmos

Thx
 
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#19
Yes, a P-channel driver will be a much better option. Make sure the driver works as you want (turns on he mosfe when your clock is low). Also, the driver will turn off much faster than the one in an earlier post.

If you want to make one from Transistors before you can order a p-channel mosfet driver, you can just add another npn inverter.

Green is current flow through load. Blue is voltage of clock.

301FEF06-B63F-494B-9D4A-85C5FCB4B246.jpeg
 
#20
Why faster? This article says N-channel is faster.
http://www.circuitstoday.com/pmos-vs-nmos

Thx
I didn't say the mosfet was faster, I said using the driver would allow the mosfet to turn off fasterthan the circuit in one suggested in another post because it included a charge trap that would not allow a mosfet to turn off quickly. Using a driver insures you don't have a charge trap. The circuit I suggest I post 19 should be fast enough for your 400Hz frequency.
 

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