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How to adjust PCIE signals using Hyperlynx S- Parameter report?

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Dear All,

I’m using Hyperlynx (MentorGraphic) for Signal Integrity test for PCIE GEN 1 Tx Rx & Clk signals. I imported Altium designed layout file to Hyperlynx. This signals (Tx, Rx, Clk) don’t pass S – Parameters when I run Serdes Batch Wizard. But it pass Channel Verification.

1. What are the changes should I do to design to pass S Parameters. How can I figure out the things need to be done using S – Parameter report?
2. Is it possible to do those changes to imported Altium design directly?
3. Why doesn’t it pass S – Parameters and but pass channel verification?

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