Edit: The timing is determined by the capacitors at the SWT and SRT pins on the MAX6302 device, the mode of that device ("extended" mode is selected in the example), the 500 nA constant current at the SWT and SRT pins, and the internal threshold voltages. Therefore, the timing is not an RC exponential type relationship, owing to the constant current charging of the timing capacitors.
The output RESET pulse width (µs) as defined in the MAX6302 data sheet is 2.67*Csrt (pF)=2674 µs.
The watchdog timeout period (µs) as per the data sheet is 2.67*Cswt (pF)=588 µs. Since the device in operated in "extended" mode, the watchdog timeout period is multiplied by 500 which gives 588 x 500=294000 µs.
Total period of oscillation is 2674+294000=296674 µs, or 3.8 Hz.
If S1 or S2 is held closed, the MAX6302 periodically outputs a reset pulse (oscillates) because the watchdog timeout interval periodically expires (by design). The RESET pulse width and the watchdog timeout interval add up to give the period of oscillation.