will allow me to place several adc devices on the same 8 bit bus for data transfer to a PIC port.
I want to be able to have them sample at the same time (triggered by the PIC) but not compete for the data bus until the pic is ready to read each adc. I believe it can be done by 'enabling' a read using the individual RD lines but it isn't clear as the line serves more than one purpose.
From the datasheet it seems clear that the outputs can be tri-stated by use of the CS input. If CS is high there will be only ~0.1uA leakage from the outputs to the data bus. The CS input has to be held low for the RD line to be effective.
Ok so with WR-RD mode set....WR pulsed low starts conversion. About 1.5uS later INT goes low indicating sample rdy, port still tri-stated. Then a RD low brings the data to the port.RD hi tri-states the PORT again. Move on to the next ADC set RD pin, pulse low etc.