list p=18F4431, b=8, c=102, n=71, t=on, st=off, f=inhx32
;******************************************************************
;* *
;* Filename: 18F4431 Boot 24.asm (v2.4) *
;* Author: Mike McLaren, K8LH (k8lh@arrl.net) *
;* Date: 18-May-05 (last rev 09-Apr-08) *
;* *
;* 18F4431 Serial Boot Loader Program (08/64 algorithm) *
;* based in part on early Microchip code examples *
;* *
;* - 8 MHz INTOSC or HS Crystal oscillator *
;* - occupies 0000-01FF code space (256 words) *
;* - RS-232 interface, 19.2 kb, <Xon> <Xoff> handshaking *
;* - inputs raw hex files which may contain code space holes *
;* *
;* MPLab: 8.01 (tabs = 8) *
;* MPAsm: 5.15 *
;* *
;******************************************************************
processor PIC18F4431
include "p18f4431.inc"
;-< radix, clock, and BRG constants >------------------------------
radix dec
clock equ 8 ; 8 MHz INTOSC
brgval equ (clock*1000000/19200/16)-1
;-< configuration fuses >------------------------------------------
if clock == 8 ;
config OSC = IRCIO ; INTOSC, RA6 and RA7 I/O
else ;
config OSC = HS ; hs xtal oscillator
endif
config FCMEN = OFF ; fail-safe clock monitor disabled
config IESO = OFF ; oscillator switchover disabled
config PWRTEN = ON ; power up timer on
config BOREN = OFF ; brown out reset enable on
config BORV = 45 ; brown out reset voltage 4.5v
config WDTEN = OFF ; watchdog timer disabled
config WINEN = OFF ; watchdog timer enable window
config WDPS = 16 ; watchdog timer prescaler
config T1OSCMX = OFF ; timer1 oscillator MUX
config HPOL = HIGH ; high side transistor active high
config LPOL = HIGH ; low side transistor active high
config PWMPIN = OFF ; PWM pin reset state control
config MCLRE = ON ; MCLR pin enabled
config EXCLKMX = RC3 ; external clock MUX bit
config PWM4MX = RB5 ; PWM4 MUX bit
config SSPMX = RD1 ; SSP I/O MUX bit
config FLTAMX = RD4 ; FLT MUX bit
config STVREN = OFF ; stack overflow/underflow reset
config LVP = OFF ; low voltage programming
config DEBUG = OFF ; background debug off
;-< code protection fuses >----------------------------------------
config CP0 = OFF ; Block 0 (000200-0007FFh)
config CP1 = OFF ; Block 1 (000800-000FFFh)
config CP2 = OFF ; Block 2 (001000-0017FFh)
config CP3 = OFF ; Block 3 (001800-001FFFh)
config CPB = OFF ; Boot (000000-0001FFh)
config CPD = OFF ; EEPROM
;-< write protection fuses >---------------------------------------
config WRT0 = OFF ; Block 0 (000200-0007FFh)
config WRT1 = OFF ; Block 1 (000800-000FFFh)
config WRT2 = OFF ; Block 2 (001000-0017FFh)
config WRT3 = OFF ; Block 3 (001800-001FFFh)
config WRTB = OFF ; Boot (000000-0007FFh)
config WRTC = OFF ; Config (300000-3000FFh)
config WRTD = OFF ; EEPROM
;-< read protection fuses >----------------------------------------
config EBTR0 = OFF ; Block 0 (000200-0007FFh)
config EBTR1 = OFF ; Block 1 (000800-000FFFh)
config EBTR2 = OFF ; Block 2 (001000-0017FFh)
config EBTR3 = OFF ; Block 3 (001800-001FFFh)
config EBTRB = OFF ; Boot (000000-0007FFh)