Hello,
I have a PLL design using 4046A that I use in our application and works fine at our frequency bandwidth ~15.25KHz. We have a new source that has slightly lower running frequency about 13.6KHz and has about 500ns phase jitter in its TTL output (compared to its master sine wave from which it is deduced, deriving TTL is done on the manufacturer supplied driver). I am trying to tune my PLL design to get stable output without any of that phase jitter and I was unable to get it stable. I guess I need to modify my existing circuit to implement new reference comparator rather than the way I am currently using. Any ideas or suggestions on improvements?
thanks
I have a PLL design using 4046A that I use in our application and works fine at our frequency bandwidth ~15.25KHz. We have a new source that has slightly lower running frequency about 13.6KHz and has about 500ns phase jitter in its TTL output (compared to its master sine wave from which it is deduced, deriving TTL is done on the manufacturer supplied driver). I am trying to tune my PLL design to get stable output without any of that phase jitter and I was unable to get it stable. I guess I need to modify my existing circuit to implement new reference comparator rather than the way I am currently using. Any ideas or suggestions on improvements?
thanks