Help needed on tuning a PLL

[pavjayt]

Hello,

I have a PLL design using 4046A that I use in our application and works fine at our frequency bandwidth ~15.25KHz. We have a new source that has slightly lower running frequency about 13.6KHz and has about 500ns phase jitter in its TTL output (compared to its master sine wave from which it is deduced, deriving TTL is done on the manufacturer supplied driver). I am trying to tune my PLL design to get stable output without any of that phase jitter and I was unable to get it stable. I guess I need to modify my existing circuit to implement new reference comparator rather than the way I am currently using. Any ideas or suggestions on improvements?

thanks

 

[dr pepper]

Its all about the loop filter with a pll.
You could slow down the response of the filter by increasing the cap, this will also increase the lock time and possibly the capture range.
You could also improve the loop filter by improving the lead/lag compensation components.

 

[pavjayt]

I am trying to use the guide mentioned here to modify my loop filter and using 74HC4046, I guess I can get some values from its **broken link removed**. How can I measure the other values that are needed in the calculations? Any help?

thanks

 

[dr pepper]

Have a look at this:

https://www.changpuak.ch/electronics/calc_04.php

Some would say designing a pll system isnt for someone without the required knowledge, but thats th ekind of thing I do all the time.

 

[pavjayt]

Thanks for that link. Actually I am using the other page on that website for calculating VCO. I calculated the values on those two links and tweaked once I had everything on the breadboard and the noise is around 10ns. I would ideally want to design a PLL based on 4046 IC using a sine wave as an input & reference at a defined frequency value within the range of (13KHz - 16KHz).

https://www.changpuak.ch/electronics/calc_03.php
R1 - 87K
R2 - 240K
C1 - 5600pF

and for VCO LPF and using the design in the link https://www.changpuak.ch/electronics/calc_04.php#
C1 - 0.1uF
C2 - 1uF
C3 - 0.01uF
R2 - 390
R3 - 3545

Using those values I am able to produce a TTL of about 10ns jitter compared to input, but when I use a sine wave input of the same frequency, the jitter is about 1us. Ideally my sine wave input's amplitude will be anywhere from 500mV to about 9V, I need to have my PLL running no matter where the amplitude is within that range. Any suggestions?

thanks

 

[dr pepper]

Might sound obvious but do you have the i/p to the 4046 decoupled with a cap, there is internal biasing in the chip so that it can handle sine wave i/p's.
If you have decoupled the i/p maybe theres an issue with the i/p circuit on the chip, you could use an op amp maybe a lm358 to square up the waveform before it goes to the pll.
That is one heck of a difference in noise, one thing I've found with this ic is that there are some big differences between manufacturer, maybe another manufacturer would have better spec.

 

[pavjayt]

Might sound obvious but do you have the i/p to the 4046 decoupled with a cap, there is internal biasing in the chip so that it can handle sine wave i/p's.
If you have decoupled the i/p maybe theres an issue with the i/p circuit on the chip, you could use an op amp maybe a lm358 to square up the waveform before it goes to the pll.
That is one heck of a difference in noise, one thing I've found with this ic is that there are some big differences between manufacturer, maybe another manufacturer would have better spec.

Yes, I do have a 0.1uF cap in series between input pin and signal. I ordered couple of different branded ones to test.