Hello to All,
I need help in Design and Program of a circuit that transmits and receives four 4-bit numbers in a multiplexed sequence along a single transmission path. The whole Project is in this site posted http://72.14.207.104/search?q=cache:uOV6A4ZIUUEJ:www.cc.ntut.edu.tw/~ymshen/Lab%252028.pdf+%22Time+Division+Multiplexing+(Lab+Project+2)%22&hl=en
so if anyone can help me, his/her help will be appreciated.
Thanks
Hello to All,
I need help in Design and Program of a circuit that transmits and receives four 4-bit numbers in a multiplexed sequence along a single transmission path. The whole Project is in this site posted http://72.14.207.104/search?q=cache:uOV6A4ZIUUEJ:www.cc.ntut.edu.tw/~ymshen/Lab%252028.pdf+%22Time+Division+Multiplexing+(Lab+Project+2)%22&hl=en
so if anyone can help me, his/her help will be appreciated.
Thanks
A state machine that feeds 4 serial to parallel converters.
FSM receiver idea:
S1: Get bit in stream send it to S2P#1
S2: get next bit send it to S2P#2
S3: get next bit send it to S2P#3
S4: get next bit send it to S2P#4
S5: Inc counter
S6: if count >=16 then DONE else S1 (start over to do next 4 bit word)
DONE: S2P's convert bits to parallel words & load into register.
Then do a transmitter by doing the reverse. To share the same dataline, have a higher level module control whether or not it is RX or TX and turn the I/O around appropriately.
Of course, not VHDL.. but I think you get the idea. It is quite simple to w rite.
Do you expect someone to provide them to you? Maybe someone will be nice enough to spend time on that. Dont you think you should try to design the VHDL yourself? If you try it yourself, post it and I'll help you work out the details. Maybe you can find something on the web if you dont want to spend time on it..people love that web out there.. :roll: