bhavik12345
New Member
Hi,
I need some help regarding the steps required to design a digital system to produce a PWM signal that produces pulses at a frequency in the range 50Hz-100Hz. The pulses will be between 1ms and 2ms duration. The actual length of the pulse will be determined by a person's name. The 1ms variation in pulse length is to be controlled by the ASCII value of the name's initials (https://www.asciitable.com/). After the first ms of the pulse the remainder of the pulse will be determined by the ASCII value of the initials. This means that the ASCII value determines the length of the pulse is that after the first ms of the remaining length should be: asci value / 256 x 1 ms. I need to produce a system that generates two pulses whose lengths are determined by first initial then two pulses whose lengths are determined by second initial, then repeating back to first initial. The system should have an input that allows you to change whether it is using the uppercase value or the lower case value of initials. This has to be done in Cyclone II FPGA using Verilog. i have a basic understanding of PWM as well as Verilog but am not that strong in HDL coding, help please.
I need some help regarding the steps required to design a digital system to produce a PWM signal that produces pulses at a frequency in the range 50Hz-100Hz. The pulses will be between 1ms and 2ms duration. The actual length of the pulse will be determined by a person's name. The 1ms variation in pulse length is to be controlled by the ASCII value of the name's initials (https://www.asciitable.com/). After the first ms of the pulse the remainder of the pulse will be determined by the ASCII value of the initials. This means that the ASCII value determines the length of the pulse is that after the first ms of the remaining length should be: asci value / 256 x 1 ms. I need to produce a system that generates two pulses whose lengths are determined by first initial then two pulses whose lengths are determined by second initial, then repeating back to first initial. The system should have an input that allows you to change whether it is using the uppercase value or the lower case value of initials. This has to be done in Cyclone II FPGA using Verilog. i have a basic understanding of PWM as well as Verilog but am not that strong in HDL coding, help please.
