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Frequency of ripple current in Electrolytic capacitor....and resultant dissipation

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Flyback

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When doing a Boundary conduction mode PFC stage, ive always gone on the thermal test of the electrolytic capacitor at the BCM PFC output as being king.

However, the current ripple in the PFC’s output capacitor has components at the switching frequency (say 70kHz). …but also has a significant component at the twice line frequency (100Hz), due to the PFC operation.

Since electrolytic capacitors have a higher ESR at 100Hz than 70khz, is it really very pertinent to actually do a FFT on the capacitor ripple current so that the power dissipation of this 100Hz component with the (increased) ESR can be found?

(When measuring the capacitor ripple current RMS on the scope over a 10ms period, it obviously just spits out an IRMS measurement, and doesn’t tell you what is the IRMS of the actual 100Hz component.)
 

ronsimpson

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To measure an approximation of the 60hz (or 50hz) ripple current with out the 70khz, try measuring the current off the power line. The low pass filter should remove much of the high frequency noise.
 

ronsimpson

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Is there data sheet evidence to support that?
Well?????
There is evidence that the maximum current (that causes 5C rise) is frequency dependent.
Going form power line frequency to switching frequency should 2X the current ability.
Notice I did not say anything about ESR.
upload_2016-12-19_18-16-34.png
Data from United Chemi-con SMR series. Just a part I pulled from stock and have used in this application. 820uF 450V
 

Tony Stewart

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The load spectrum is what counts below the PWM rate. What is the % max load step. Then an ripple pulse wil be the spectrum of the pulse ( full spectrum unless recurring) times the current times the spectrum of ESR from 10 Hz. Minimum ESR is near SRF of the cap and ESR*C can be << 1uS or >>1ms depending on size and design, quality,
 

Tony Stewart

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Hey Flyback what they do on LiPo cells with EIS (spectogram) similar to a network analyzer or Bode Plot show ESR, Reactance and impedance vs Capacity vs frequency we could get more precise ESR vs f values. They are generally fairly flat but reduce slightly from benefits of skin effect with rising frequency , lower ESR until resonance.

Also ESR has a size dependancy for e-caps. I took one datasheet and plotted a bunch of values with different sizes at same voltage for the room temp values. diameter, D x length, L (actually height) or DL product, then computing the C(uF)/DL ratio matches ESR on a log scale.

upload_2016-12-20_17-35-48.png
 

Tony Stewart

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Flyback The other critical function is decoupling nanosecond spikes caused by CMOS and FR4 10nH/" with 2pF/" for typical trace widths which of course depends on return path ground plane and also depends on ESR of the cap which if too low can cause serious anti-resonance. ( supported by Murata ceramic caps)

So I did thuis quick analysis today of one CMOS unbuffered inverter with 1" of FR4 using 74HCxx driver impedance of 50 Ohms nominal @ 5V to show much more supply spikes are critical now than the old CD4xxx series with high ESR. I added other stuff to make it a ring oscillator.

This of course can be suppressed with carefully chosen SMT ceramic caps on each IC or clever thin dielectric Vss,Vdd plane for buried capacitance and triple vias for low ESL.
Someone asked me why 2% ripple was a system spec for CMOS . I deferred to ATX specs and MOBO faults which support my own experience.

With no pwr gnd plane on FR4.... and nearest decoupling 1 inch away on next IC.
Here's what I got,. the 5V supply is 0 ESR and so the 10uF is just for show. Now examine Vss, Vdd noise.
upload_2016-12-20_18-0-57.png
 

Flyback

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I understand that when there is a low frequency envelope which modulates the high frequency waveform that flows in an electrolytic capacitor then the increased ESR must be considered for the low frequency component. (because as you know, electrolytic capacitor ESR is always higher for the lower frequencies)

….However, is this really true?....for example, consider a 100khz Flyback power supply running constantly for 2000 days. Now consider that for one day it is run at full load, then for the next day it is suddenly switched to run at half load, then suddenly back to full load….etc etc , continuously. So what we have is a modulating envelope in the electrolytic capacitor ripple current that has a period of 1 day. Now, from our theory concerning that ESR is greater for lower frequencies…would we have to consider the increased ESR for the 1 day period component?

I suspect that we would not……however, the 1 day period component is definitely there.

So I suspect that low frequency modulating envelopes of high frequency capacitor ripple current do not actually have to be taken into account in the assessment of the actual ESR. Do you agree?
 

spec

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I understand that when there is a low frequency envelope which modulates the high frequency waveform that flows in an electrolytic capacitor then the increased ESR must be considered for the low frequency component. (because as you know, electrolytic capacitor ESR is always higher for the lower frequencies)

….However, is this really true?....for example, consider a 100khz Flyback power supply running constantly for 2000 days. Now consider that for one day it is run at full load, then for the next day it is suddenly switched to run at half load, then suddenly back to full load….etc etc , continuously. So what we have is a modulating envelope in the electrolytic capacitor ripple current that has a period of 1 day. Now, from our theory concerning that ESR is greater for lower frequencies…would we have to consider the increased ESR for the 1 day period component?

I suspect that we would not……however, the 1 day period component is definitely there.

So I suspect that low frequency modulating envelopes of high frequency capacitor ripple current do not actually have to be taken into account in the assessment of the actual ESR. Do you agree?
Hi FB,

What you say is essentially true but, by taking values to extremes, you can arrive at some non-representative conclusions.

If you have a sine wave (Fc) amplitude modulated by another sine wave (Fm), the resulting modulated signal will comprise, Fc + (Fc-Fm) + (Fc+Fm). For a square wave the principle is similar, except multiple frequencies will be involved.

In the example you cite, Fc is 100KHz, but Fm is only 6 micro Hz (6 * 10^-6) so, in practical terms, the only frequency seen by the capacitor is Fc (100Khz).

The reactance of a capacitor does drop with frequency due to the formula, XC = 1/(2 * Pi *F * C) but, when the various non-ideal factors come to play, the impedance (Z) rises. In fact, pretty much all components, including PCB traces and resistors, turn unto inductors at some point in the frequency spectrum. A 50 Ohm metal film resistor becomes an inductor at around 200MHz, if I remember correctly.:)

spec
 
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Flyback

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What you say is essentially true but, by taking values to extremes, you can arrive at some non-representative conclusions.
Thanks, -it depends on what you call an “extreme”. As you know, the low frequency envelope is actually 23.1uHz. The point is, as you know, Who says that this is an “extreme”? Is a day an extremely long period of time to a capacitor with regards to its ESR?

And if 23.1uHz is an extremely low frequency, and means that the ESR component at that frequency should not be considered, then what is the lower bound of frequency which the capacitor “recognises” as a low frequency ripple component?
 

spec

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On a general point about capacitor dissipation: where multiple complex wave-forms are involved you can get involved in loads and loads of calculations which, for various practical reasons, bear little resemblance to the actual dissipation in a circuit. So it is always best to do an acid test and measure the capacitor temperature to get a feel for what is going on.

spec
 

Flyback

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Thanks, the problem is that we are using big capacitors, (7cm height radial with 3cm radius) and the temperature at the case may be well below the temperature deep down in the electrolytic.
Also, we have a capacitor charge/discharge application, and we have two ways of charging it, and one way involves a low frequency envelope.....we want to use the method that dissipates as little as possible in the capacitor. -So we'd like to be able to calculate dissipation first....but we dont know what ESR value to use for the low frequency modulation envelope.
As you will know, it will take much time to keep making prototypes and testing them thermally......we woudl like to be able to make the least dissipation solution. (but as you know we will do thermal testing on that anyway)
 
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spec

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Thanks, -it depends on what you call an “extreme”. As you know, the low frequency envelope is actually 23.1uHz. The point is, as you know, Who says that this is an “extreme”? Is a day an extremely long period of time to a capacitor with regards to its ESR?

And if 23.1uHz is an extremely low frequency, and means that the ESR component at that frequency should not be considered, then what is the lower bound of frequency which the capacitor “recognises” as a low frequency ripple component?
All frequencies are recognized by a capacitor, but the reactance (Xc) at 23.1 micro Hz (or 6 micro Hz) is so high that practically no current flows and thus capacitor heating is insignificant.

What is significant depends on the application and is open to interpretation. But, in general, you could say that any frequency that contributed 1%, or less, of the permitted ripple current would be insignificant.

spec
 

Flyback

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All frequencies are recognized by a capacitor, but the reactance (Xc) at 23.1 micro Hz (or 6 micro Hz) is so high that practically no current flows and thus capacitor heating is insignificant.
Thanks, it would be good to know what the ESR actually is at the lower frequencies. Our actual application has a 1Hz low frequency envelope and we wonder how much the ESR will be for that.
The cap is charged up over one second, then a xenon lamp is flashed, then it charges up over and over after each flash. The actual current of charge is the output of a 70khz flyback. We wonder how much the 1Hz component will be significant. Also, there is a 100Hz envelope in there too since the flyback has a mains input without a primary side electrolytic capacitor.
 

spec

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Thanks, the problem is that we are using big capacitors, (7cm height radial with 3cm radius) and the temperature at the case may be well below the temperature deep down in the electrolytic.
Wow! Those are big capacitors, but not unreasonably so. The core temperature will be well below the can surface temperature, but you should be able to get the thermal resistance, core to case, from the capacitor datasheet or direct from the manufacturer.

Also, we have a capacitor charge/discharge application, and we have two ways of charging it, and one way involves a low frequency envelope.....we want to use the method that dissipates as little as possible in the capacitor. -So we'd like to be able to calculate dissipation first....but we don't know what ESR value to use for the low frequency modulation envelope.
It depends how low the frequency is. If it is low enough you can forget it.

You will be putting the same charge into the capacitor whichever charging method you use, and I think, with that caveat, that the minimum heat would be achieved by a constant current charge, or close.

As you will know, it will take much time to keep making prototypes and testing them thermally......we woudl like to be able to make the least dissipation solution. (but as you know we will do thermal testing on that anyway)
Yes testing does take time.:eek:

spec
 

spec

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Thanks, it would be good to know what the ESR actually is at the lower frequencies. Our actual application has a 1Hz low frequency envelope and we wonder how much the ESR will be for that.
The cap is charged up over one second, then a xenon lamp is flashed, then it charges up over and over after each flash. The actual current of charge is the output of a 70khz flyback. We wonder how much the 1Hz component will be significant. Also, there is a 100Hz envelope in there too since the flyback has a mains input without a primary side electrolytic capacitor.
Hmm, a flyback converter only provides current for half of the switching waveform. The heating would be less if you could arrange for a constant current for the period that the capacitor is charging.

But the discharge current will almost certainly cause the most dissipation and stress the capacitor the most (dv/dt and di/dt) and there is nothing you can do about that as it is a design requirement.:)

spec
 

spec

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Just a thought, you are using an electrolytic capacitor but you don't say what value or what voltage you are charging it to (or have I missed it).

But you will probably benefit from connecting a large polypropylene capacitor across the electrolytic capacitor.

spec
 

Flyback

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Hmm, a flyback converter only provides current for half of the switching waveform. The heating would be less if you could arrange for a constant current for the period that the capacitor is charging.
Thanks, though if it was a constant current recharging every second, then that would be a high ESR, as the frequency of the current would be very low.
 

Flyback

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the cap gets charged up from 60v to 300v.......it then powers the xenon for about 1ms, and tumbles down to 60v again
 
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