It's an external SARs ADC that takes 24 clock cycles per sample, with a clock up to 4.8MHz (maximum 200ksps). Don't I just have to make sure the clock edges rise and fall together? If you are referring to synching the filter clock with sampling intervals, isn't that implied since sampling only ever starts at the beginning of a clock pulse? Unless you are referring to how the ADC can sample many many times faster than the filter's switched capacitors will switch- in which case I have no idea how you would pull off the synching.
I'm going to also be doing this with a sigma delta ADC later on, and the sampling frequency is way way higher, even though the output is only 480sps, the actualy sampling is in the about 300khz.
How do you synch the clock of the filter with an internal ADC? Or do you derive it from the uC clock?
EDIT: Sincce you said switched-capacitor, it turns out that's the term I needed to describe the filter-ADC mating for a proper search. I came up with this article:
**broken link removed**
I think it explains it, but I haven't actually read it yet since I'm busy playing a game.