Filters & ADCs- Clock Synching & Beats

[dknguyen]

I have a switched-capacitor filter and an ADC chip. The switched cap filter uses a clock signal to set the cutoff frequency. The datasheet says:

"When using the MAX7401/MAX7405 for anti-aliasing or
post-DAC filtering, synchronize the DAC and the filter
clocks. If the clocks are not synchronized, beat frequencies
may alias into the passband."

I'm not sure what this means though...since the ADC clock is working at 4MHz and the filter clock is only working at 50khz. I'm not sure if it matters in this case because the only thing I know about synching clocks are clock distribution chips out there which seems excessive since those are for large systems.

 

[mvs sarma]

Hi,
Beats on mixing two frequencies of nearly equal value is a known phenomenon in analog electronics. imagine the difference being 2Hz the you hear for example two frquencies are 800Hz and 798Hz you hear a sond increasing and reducing in volume and rate of variation will be at f1-f2.

coming to 4Mhz and 50Khz, later isa subharmonic of 4Mhz. thus the Nth harmonic of 50Khz beats with 4MHz, being close to it. it can pehaps be managed by deriving 50Khz from 4Mhz.

regards

 

[Sceadwian]

The ADC clock might be working at 4mhz, but what you need to know is the actual sample rate of the ADC. No micro controller I know of has an ADC that actually samples at the ADC clock rate, it's usually MANY MANY times slower.
Speaking from experiance with Atmels AVR series of chips and their ADC's The maximum sampling frequency is only around 20khz tops, and that's on a 16mhz chip. Or are you using an external ADC rated at 4mhz sampling rate?

 

[dknguyen]

It's an external SARs ADC that takes 24 clock cycles per sample, with a clock up to 4.8MHz (maximum 200ksps). Don't I just have to make sure the clock edges rise and fall together? If you are referring to synching the filter clock with sampling intervals, isn't that implied since sampling only ever starts at the beginning of a clock pulse? Unless you are referring to how the ADC can sample many many times faster than the filter's switched capacitors will switch- in which case I have no idea how you would pull off the synching.

I'm going to also be doing this with a sigma delta ADC later on, and the sampling frequency is way way higher, even though the output is only 480sps, the actualy sampling is in the about 300khz.

How do you synch the clock of the filter with an internal ADC? Or do you derive it from the uC clock?

EDIT: Sincce you said switched-capacitor, it turns out that's the term I needed to describe the filter-ADC mating for a proper search. I came up with this article:
**broken link removed**

I think it explains it, but I haven't actually read it yet since I'm busy playing a game.

 

[Sceadwian]

There is absolute nothing to say you're using the same clock source to drive your ADC as you are your filter. And clock riseing and falling together is EXACTLY what sync means. It's called phase, look it up =) Even a few fractions of a hertz out of phase sync between the two can cause weird signals to be measured at the output. Slowly or quickly rising transient tones that appear and disappear seemingly out of nowhere.

 

[dknguyen]

In our digital world, 1hz is a very long time! I was just wondering what you meant by needing to know the sample rate more than the actual ADC clock. What does the sample rate have to do with synching filter+ADC clocks? I know I don't have to use the same clock- just how the clocks are supposed to be synched together.

I'm kind of wondering if I should do:

1. sensor->buffer->filter->buffer->ADC
2. sensor->filter->buffer->ADC
3. sensor->buffer->filter->ADC

I don't seem to have gain-bandwidth data or slew rate data for the filter to know if it can properly drive the ADC. I don't think I need (1) as long as I keep the cutoff high enough to keep the input impedence of the filter low. But I am wondering if having an op-amp buffer between the filter and ADC affect the clock synching (or maybe it eliminates the need for it?). I'm not sure.

 

[Nigel Goodwin]

The design of the filter may mean you don't require buffers?, it depends on it's input and output impedances and the source and load requirements.

 

[dknguyen]

Here is the email I fired off to Maxim:

Hello. I am using the MAX7401 (or 5th order switched capacitor
filters series) for anti-aliasing of an ADC input. The ADC is the
MAX1068 or MAX1168. There will be two versions of this circuit-
one with a source output impedence of 32k and the other with an
output impedence of 180k. The filter cutoff will be 500Hz or
less. Therefore I am fairly certain a buffer is not needed
between source and filter.

1. In a App Note 3494, it is said that an RC-filter is needed to
prevent aliasing due to the switched-capacitor sampling of the
filters. This appears nowhere in the filter datasheets so I am
wondering if it is always necessary and under what conditions it
would be necessary.

2. My primary question is whether or not a buffer is needed
anywhere along the signal chain. Since my bandwidth is 500Hz
maximum, it would seem that the input impedence is sufficiently
high for my sensor output impedences. But I do not know if the
filter itself is able to drive the ADC properly.

The MAX1068/1168 datasheet specifies a buffer of at least:
-10MHz gain-bandwidth product
-2V/us slew rate

But none of this information is available for the filter. What is
known:

-MAX1068/1168 input capacitance is 45pF typical.
-the filter can drive 10k, 50pF load worse case (1k, 500pf
typical)

I am unsure if these numbers are equivelant to the 10MHz
gain-bandwidth product and 2V/us slew rate required for the
fubber as specified in the MAX1068/1168 datasheet.

THanks