wannaBinventor
Member
I have been playing with my enhanced midrange 16F193X PICs as I have found time. At first, the new MOVIW and MOVWI commands through me for a loop, but I think I have them now.
I've written a program that uses both File Select Registers to indirectly address one set of data and then write it to another location by use of the other FSR, with both being used at the same time. I have the numbers 1 through 5 in some globally addressable RAM and then I use both FSRs with post increment to fill the numbers over and over again until it runs out of RAM. The beauty here is that the linear addressability allows me to fill 240 bytes of RAM without ever changing banks. On a beefier enhanced midrange, one could read or write around 1K bytes of RAM without ever changing banks.
The program doesn't do anything at all, but I hope it will be useful to some others who are looking to play with these newer PICs that are having trouble understanding some of the more difficult RAM addressing techniques.
I've written a program that uses both File Select Registers to indirectly address one set of data and then write it to another location by use of the other FSR, with both being used at the same time. I have the numbers 1 through 5 in some globally addressable RAM and then I use both FSRs with post increment to fill the numbers over and over again until it runs out of RAM. The beauty here is that the linear addressability allows me to fill 240 bytes of RAM without ever changing banks. On a beefier enhanced midrange, one could read or write around 1K bytes of RAM without ever changing banks.
The program doesn't do anything at all, but I hope it will be useful to some others who are looking to play with these newer PICs that are having trouble understanding some of the more difficult RAM addressing techniques.
Code:
;THIS PROGRAM JUST TESTS THE INDIRECT FILE ADDRESSING OF MEMORY ON THE EENHANCED MIDRANGE USING THE
;TWO DIFFERENT FSRs. THIS WILL GENERATE A 1 THROUGH 5 CONSECUTIVELY IN ALL RAM LOCATIONS EXCEPT THOSE
;THAT ARE IN GLOBAL LOCATIONS, AS THEY ARE NOT LINEARLY ADDRESSABLE BECAUSE THEY CAN BE DIRECTLY
;ADDRESSED FROM ANY BANK
;********************************************************************************
;Set up the assembler options
LIST p=16F1934, r=DEC
#include <P16F1934.inc>
__CONFIG _CONFIG1, _MCLRE_OFF & _WDTE_OFF & _FOSC_INTOSC
__CONFIG _CONFIG2, _LVP_OFF & _PLLEN_ON ;& _IESO_
;********************************************************************************
;VARIABLE DECLARATIONS
;********************************************************************************
COUNTERA EQU 0x70
COUNTERB EQU 0x71
COUNTERC EQU 0x72
NUMERATOR EQU 0x73
DIVISOR EQU 0x74
REMAINDER EQU 0x75
MULTIPLIER EQU 0x76
TEST1 EQU 0x77
TEST2 EQU 0x78
TEST3 EQU 0x79
TEST4 EQU 0x7A
TEST5 EQU 0x7B
ANSWER EQU 0x7C
FSRPOINTER EQU 0x7D
COPY1 EQU 0x20 ;START OF BANK0 RAM
COPY2 EQU 0x21 ;END OF BANK0 RAM
COPY3 EQU 0x22
COPY4 EQU 0x23
COPY5 EQU 0x24
COPY6 EQU 0xA0 ;START OF BANK1 RAM
COPY7 EQU 0xEF ;END OF BANK1 RAM
COPY8 EQU 0x120 ;START OF BANK2 RAM
COPY9 EQU 0x16F ;END OF BANK2 RAM
;********************************************************************************
;Vectors
ORG 0
goto INITIALIZEPIC
ORG 4
retfie
;Start of program memory page 0
ORG 5
;********************************************************************************
;SUBROUTINE SECTION
;*********************************************************************************
INDF0_RESET
MOVF FSRPOINTER,W
MOVWF FSR0
RETLW .0
;********************************************************************************
;INITIAL CONFIGURATION SECTION
;********************************************************************************
INITIALIZEPIC
BANKSEL OSCCON
MOVLW B'01110000' ;32mhz oscillator
MOVWF OSCCON
bcf ADCON0,ADON
bcf ADCON1,ADFM
banksel ANSELA
MOVLW B'00000001' ;SET UP PORTA FOR ANALOG INPUT
MOVWF ANSELA
clrf ANSELB
banksel CM2CON0
bcf CM2CON0,C2ON
bcf CM1CON0,C1ON
banksel PORTA
clrf PORTA
clrf PORTB
clrf PORTC
clrf PORTD
clrf PORTE
banksel TRISB
MOVLW B'00000001' ;SET UP PORTA FOR ANALOG INPUT
MOVWF TRISA
CLRF TRISB
CLRF TRISC
BANKSEL ADCON0
MOVLW B'00000001' ;AN0 CHANNEL SELECTED, ADC PERIPH ON
MOVWF ADCON0
MOVLW B'00100000' ;LEFT JUSTIFIED, FOSC/32, RAIL REFERENCE
MOVWF ADCON1
BANKSEL TEST1
MOVLW .1
MOVWF TEST1
MOVLW .2
MOVWF TEST2
MOVLW .3
MOVWF TEST3
MOVLW .4
MOVWF TEST4
MOVLW .5
MOVWF TEST5
MOVLW 0x77
MOVWF FSRPOINTER
;*****************************************************************
;Start of the main program
;*****************************************************************
;THIS PROGRAM JUST TESTS THE INDIRECT FILE ADDRESSING OF MEMORY ON THE EENHANCED MIDRANGE USING THE
;TWO DIFFERENT FSRs. THIS WILL GENERATE A 1 THROUGH 5 CONSECUTIVELY IN ALL RAM LOCATIONS EXCEPT THOSE
;THAT ARE IN GLOBAL LOCATIONS, AS THEY ARE NOT LINEARLY ADDRESSABLE BECAUSE THEY CAN BE DIRECTLY
;ADDRESSED FROM ANY BANK
START
MOVLW 0x77 ;THIS IS IN GLOBALLY ADDRESSABLE RAM, SO IT CAN'T BE LINEARLY ADDRESSED
MOVWF FSR0
MOVLW 0x20 ;FSRn at 0x2000 access bank 0 ram loc 20h.
MOVWF FSR1H
MOVLW 0x00 ;finish loading FSR1
MOVWF FSR1L
COPY
MOVIW INDF0++ ;move contents of indirectly addressed register to W, post increment
MOVWI INDF1++ ;move W to indirectly addressed register, post increment, this creates an indirect copy
MOVF FSR0,W ;copy FSR0 into W for a test
SUBLW 0x7C ;see where this is at 7B was last meaningful location being copied from, so with post inc it is at 7C when meaningless locations are reached
BTFSC STATUS,Z ;if RAM location 7C is yet the value of FSR0, skip next line
CALL INDF0_RESET
MOVF FSR1H,W ;move FSR1 high to W for a test
SUBLW 0x20 ;this is high byte of FSR1
BTFSS STATUS,Z ;if equal to 20h, skip next line
GOTO COPY
MOVF FSR1L,W ;go BACK to top and keep going
SUBLW 0xF0 ;0x20F0 is the last linearly addressable RAM location that gets shadowed in GPRs on the 16F1934
BTFSS STATUS,Z ;so, when we get here we need to stop copying or else we will cause a crazy wrap around
GOTO COPY ;if we arent at 0x20F0 yet with FSR1, keep copying
ENDLOOP
GOTO ENDLOOP
;*****************************************************************
;Start of program memory page 1
ORG 2048
END