As, after you select parts and complete schematics (Cadence Orcad 10.5), the first thing is to verify schematics, then assign the footprints and then create a netlist. After that you go to Layout, you define the board size and shape. After that you define the constraints i.e. define track width(according to Signal type i.e high frequency/ High current etc), track to track, track to pad, pad to pad, pad to via, via to track parameters.
After that you define the layer padstacks, components padstack and the number of layers to be used. For your case it will be bottom layer only. if jumpers are required then define Top layer to act as jumper layer. As you complete routing run Design Check Rule (DRC). As drc verifies produce Gerber files and take a look of it in any Gerbview software.
Take the prints out (Mirrored view) or you can develop a film from any screen printer to develop your pcb. Etch the board in Ferric chloride solution. A common mistake often found in such boards is that too thin tracks have often dicountinuties or have a higher impedance so a general rule to be followed is that track width should not be less than 25mils. Or if you pcb design constraints are tight (track width less than 20 mils, SMD components etc etc) enough better to consult a low cost PCB manufacturer. Hope this would help you.