digital clock logic gates and ic design

how can we design digital clock with MAX+PLUS2 10.2 baseline?
i have no idea how to produce the 1pps.
i have to design the circuit using logic gates and flip flop and ic.
anybody have the knowledge?

i think you would hve to make a astable using inverter (or nand gates made into inverters) to make a second pulse then a bcd counter/decoder to show this, then a logic gate system or another astable to to work a seconds counter/decoder.

The usual way is to use a 32.768kHz crystal. This frequency is convenient because it's 2^15Hz so you can divide it down to 1Hz with a 15 bit counter.

Other than that you just need some counters for seconds Hours Days and some BDC and 7 segment decoders.