The idea is to have less dedicated peripherals and let each cog be an "intelligent" peripheral. Each cog could probably implement a couple serial channels, spi, rs232, or whatever protocol, or generate a video signal, or just do general processing. This one chip could probably generate multiple video streams simultaneously...
Say you want to create a jitter free RC servo signal - a cog could probably generate a couple servo's worth of signals just sitting there in a tight loop counting clock cycles and doing nothing else. Then for the interface, you have another cog bit-banging the UART and doing all the slow and complex command parsing.
This chip is just too different from standard approaches to be "practical" in most applications, but from the hobby perspective, this is a really amazing chip/approach.