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Diagram of a 8051 Digital IO pin.

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alphacat

New Member
Hello.

I have a 8051 Uc and I can configure the Digital I/O pins to be one of the several options below:
1. Input with an internal pull-up.
2. Input with an internal pull-down.
3. tri-state.
4. 1L output.
5. 0L output.

How does a diagram of such pin looks like?

Thank you.
 

Sceadwian

Banned
What do you mean diagram? You just listed all the options so that's what your diagram would look like.
 

Papabravo

Well-Known Member
Hello.

I have a 8051 Uc and I can configure the Digital I/O pins to be one of the several options below:
1. Input with an internal pull-up.
2. Input with an internal pull-down.
3. tri-state.
4. 1L output.
5. 0L output.

How does a diagram of such pin looks like?

Thank you.
Such a diagram is pretty common fare for a manufacturer's datasheet or hardware manual. Do you have one? Can you find one? Do you need me to hold your hand and give you a link?

BTW which 8051 variant can source current in the high state or be configured with a pull-down?
 
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Sceadwian

Banned
I was wondering the same thing myself, pull-downs aren't common.
 

alphacat

New Member
Hey,

@Papabravo:
The spoken 8051 Uc is CC2430.
In its datasheet, there's no diagram for how its implement electrically.
(There's only diagram there of interrupts, but it doesnt mention there the pull-up/downs, input/output configuration).

@Sceadwian:
I know how its described verbally, but i dont know how its plotted.
Therefore i'd love to see such diagram.
 

alphacat

New Member
--
For example, i know how to *program* the Uc's pin to be pull-up connected, or pull-down connected (in case its configured to be an input), but i dont know how its done electrically.
 
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Papabravo

Well-Known Member
I see the problem now. The CC2430 has an 8051 core, but it does not have 8051 compatible I/O pins. You are correct in stating that there is no diagram.

One possible way to do pullups and pulldowns on the inputs it is:

On an input a pullup is implemented with a weak p-channel FET that has from 20K to 40K ohms of channel resistance. The gate of this p-channel FET is connected to a register bit which can be enabled by the program. The pulldown is implemented in a similar way with an n-channel FET having 20K to 40K of channel resistance.

Another key difference is that the pins have symmetrical output drive which is definitely NOT 8051 compatible.
 
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