Vbat = 9V, so T1 (now a pnp transistor) base current can flow only when the base is less than ~8.4V. When the external voltage is >8.4 the transistor is turned off (no base current), so the collector voltage is pulled down by the 47k resistor towards 0V (it will only reach 0V if the AVR input pull-up is infinite resistance, which is why I said the AVR circuitry might need to be altered).
Assuming the external voltage is normally 12V, if it suddenly drops then the cap will discharge through the 470k resistor. The time to drop from 12V to 8.4V (a fraction of the 100 secs; it depends on V+ but lets say 30 secs) is the delay you get before the alarm trips. At 8.4V base current begins to flow and collector current raises the collector voltage (J3-4) to ~9V.
So the answers to your questions are
1) logic 1 (actually ~9V, so a tap half-way down the 47k resistor would be needed if the AVR runs at 5V)
2) logic 0, provided the AVR pull-up is > ~ 100k,
3) logic 1, provided V+ < 8.4 and delay expired, otherwise logic 0 if AVR pull-up > ~ 100k