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CPLD (Xilinx) programming tutorial

Thread starter #1
How to start with programmable logic.
1. You'll need a PC with a parallel port (true parallel port, no USB adapters)
2. Download and install the Xilinx ISE Webpack from www.xilinx.com
3. get/buy/build the Xilinx Parallel cable III programming adapter
4. get a Xilinx CPLD, for example XC9572 in PLCC-44 package
you can also buy a PLCC-44 to DIP adapter (e.g. Aries, from DigiKey) and
use breadboard.

When programming a CPLD (or FPGA) you don't create a program but description of the logic that implements the desired functionality, usually using a hardware description language. I will use VHDL in the example.

Example #1: Implement a synchronous 4-bit counter with asynchronous reset and synchronous load (a little like a simplified 74161) signals active in '1', clock at rising edge.

Create a new project, select directory and top level source HDL, Next>
Select device (XC9572) and package (PC44) preferred language VHDL.
Then you can use the wizard to create a new source (mycounter.vhd)
and implement the logic - copy the VHDL code from below:
Code:
-- includes (common useful libraries)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- tutorial: 4 bit counter design
entity Mycounter is
    Port ( reset 	: in  std_logic;		-- asynchronous reset
           clk 	: in  std_logic;     -- master clock input, active rising edge
           load 	: in  std_logic;     -- synchronous load enable
           data 	: in  std_logic_vector (3 downto 0); -- data to load if load is '1'
           output : out  std_logic_vector (3 downto 0)); -- output of the counter
end Mycounter;

architecture rtl of Mycounter is
	
	-- VHDL does not allow using output signals as input so I need this helper signal
	signal	myout: std_logic_vector(3 downto 0);

begin
	
	-- send out helper signal to the output pins
	output <= myout;
	
	-- this is the output signal
	cntr: process (reset, clk)
	begin
		if	reset = '1' then
			myout <= "0000"; -- reset active ...
		elsif rising_edge(clk) then -- no reset, so wait for rising edge of the clock
			if load = '1' then
				myout <= data; -- load was active so copy input data to the output
			else
				myout <= myout + 1; -- load was not active so count ....
			end if;
		end if;
	end process cntr; --- that's all
	
end rtl;
Then you can run the implementation (Menu Process/Run) and if everything is ok, a programming file for the CPLD is created. The only problem is we don't know which pins are the signals load, data ....

So let's add another file - User constraints file (.ucf) where we force the implementation to use specific pins for our signals
Click on the left side Create new source and select implementation constraints, name it MyCounter.ucf. Here is my selection of pins:
Code:
NET "clk"        LOC = "P5" ;
NET "data<0>"    LOC = "P1"  ;
NET "data<1>"    LOC = "P2"  ;
NET "data<2>"    LOC = "P3"  ;
NET "data<3>"    LOC = "P4"  ;
NET "load"       LOC = "P44"  ;
NET "output<0>"  LOC = "P12"  ;
NET "output<1>"  LOC = "P11"  ;
NET "output<2>"  LOC = "P9"  ;
NET "output<3>"  LOC = "P8"  ;
NET "reset"      LOC = "P39" ;
There are specialized pins optimized for clock input (GCK) and for global reset (GSR) so I used them, other pins I just chose what was conveninent ....
Now it is time to run implementation again and them to program the CPLD.

To program the programming file into the CPLD connect the JTAG pins of the CPLD to the programming adapter, power the CPLD and adapter (5V for XC9500 family and 3.3V for XC9500XL family). Expand the Generate Programming File and select Configure Device (iMPACT). Use the default options.
After programing the CPLD you can connect it on a breadboard and check that it performs the designed function - a 4-bit binary counter :)

Enjoy.

Petr
 
Thread starter #3
The short answer is your cheap JTAG interface will not work unless made specifically for Xilinx CPLDs. Additionally the one you gave on that page is maybe affordable but at $119 is definitely not cheap - the parallel interface will cost you literally just a few $ if you build it yourself AND is directly supported from inside the development environment. Actually it should be possible to use a JTAG adapter supporting SVF format but this involves extra step (converting the jedec programming file to the SVF format by redirecting the output of the JTAG programmer to a file). If you really do not want to build the Xilinx JTAG parallel port adapter (which is really simple, just two 74HC125 and a few passive components) I can suggest to look at http://www.digilentinc.com they have a lot of interesting items for programmable logic (for example their NEXYS 2 board)
and also JTAG USB cable for $38 which supports Xilinx devices and also Atmel AVRs

http://www.digilentinc.com/Products/Detail.cfm?Prod=JTAG-USB&Nav1=Products&Nav2=Cables

BTW the Nexys 2 board already contains this adapter so if you own NEXYS 2 you just connect it via USB to your PC and install their software.

The reason why I have suggested the parallel port JTAG interface is that it is really the cheapest solution and the only one supported directly from the Xilinx development environment. The Xilinx USB JTAG is unfortunately quite expensive.
 
#4
Oldish thread but still relevent; thanks petrv for the useful tutorial which contributed to my decision to buy the xc2-xl board from digilent via digikey. As per your last post it includes the parallel jtag cable [but not the listed printed manual]. Good value for about forty quid.

There are a couple of bugs to work out:- chip selection jumpers on board are wrong way round [digilent] and PACE will not work with spaces in directory names [xilinx] -: not ideal for a first timer, but now that I know I'm making progress.
 
Thread starter #6
Hi monkeybiter,

I am glad you found my tutorial useful, yeah I did not mention you should not make spaces in directory names (I would never do that anyway, IMHO spaces are not good idea in file or directory names ...) But I think xc2-xl is obsolete board - it can be useful if you really want to work only with CPLDs but NEXYS 2 board with FPGA is *MUCH* more powerful - especially the one with the bigger FPGA is one of the best deals when you want to but a board for programmable logic. CPLDs are fine for simple logical designs but unfortunately they are quite limited for more complicated sequential logic by the number of flip-flops available (XC9536 has 36 flip-flops, XC9572 has 72 flip-flops etc ...)
compare that with FPGAs that has many thousands of flip-flops - it is easy to put inside complete logic for a system-on-chip, for example I have made a FPGA version of the famous British 8-bit computer ZX-Spectrum which fits in 500k FPGA - once you learn to work with programmable logic and especially with FPGAs you will see how much more they are powerful compared e.g. to microcontrollers.

Petr
 
#7
I think xc2-xl is obsolete board
It was the best deal for my limited budget for a first taste of PL. So far I'm liking it and may spring for an FPGA board when I can afford it.
A few months ago I bought 6 XC9572's [5V] on EBay. I'll have a go with them when I get up the nerve to try soldering TQFP !
 
Thread starter #8
Well, enjoy !

I have actually 2 FPGA boards and for CPLD I bought the PLCC version of XC9572 and put them in a socket (look at DigiKey.com - Aries PLCC44 to DIL adapter). Actually XC9572XL (3.3V version) is significantly cheaper than the 5V version and it still has 5V tolerant I/O pins so you just need to get a 3.3V power supply which is easy with LDO like LM1117 or LD1117.
The two FPGA boards I have are XESS XSA-3S1000 (1 mil. gates) and Spartan 3E starter board (500k gates). Today I'd buy Nexys 2 but that board did not exist 2.5 years ago when I bought my 2 boards. The smallest Spartan 3E FPGA has 100k gates (and costs less than $10 !) so any Spartan 3E board is quite powerful but for really complex SoC designs it is good to have at least a 500k FPGA. I have never run into a "too small FPGA" problem yet - even tried to synthetize Intel 8086 core. CPLDs are good for a simple glue logic or a small controller (not too "clever"). But the nice thing is that you can use the same tool set (ISE Webpack) and VHDL for programming both.

Petr
 
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#9
Here is an add-on for the XILINX programming hardware.

The schematic is the XILINX recommendation.

Eagle files can be obtained free via email.

Hans
Hi do you know if the Parallel Cable III fits for the Virtex XC2V2000 and the XC2V1000 FPGA`s? If affirmative could you send me the Eagle files?
 
#11
Avnet Spartan-3A Evaluation Kit

Buy one of these. Comes with an amazing 60 page tutorial on how to program it that includes pictures and details for your first FPGA/Verilog program. All for $50.

But that's not for the CPLDs, is it ? Looks like it is just for the FPGAs.

I need to be able to program the 9500 series CPLDs and "true" parallel ports are obsolete. Yes, I do have one or two on old computers, but saving $100.00 is not a good reason, typically these days ? Well, not for me anyway.

How much does the Xilinx programmer cost ? I guess I better look for it.
... IF I can find it.

boB
 
#13
Sorry for the thread necromancy. This thread came up on a Google search. I just wanted to add that Xilinx sells CoolRunner II development kits for $35 which includes the ability to program the CPLD using a USB cable. When I got mine it also came with a very nice LCD display.
 
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#15
Those are some great deals on basic kits. I just scored a cyclone II kit from e-bay for $112. The technology is considered "obsolete" becuase it goes all the way back to 2005, but it was actually the same technology that was used by Altera to validate the designs I"m presently working on, and I saved a considerable amount of money from the $1500.00 kits they are presently selling.
 
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#16
I"m not exactly sure what this kit does for me. Also, looks like they are out of stock on this item from that page.

We are presently using the XC9536XL CPLD. Do you think that Xilinx has a power supply pin compatible part with more innards in that same package ?? Do you think that the Coolrunner kit would program a XC9546XL part ? I wouldn't mind looking at a part that had more capability but where I didn't have to change our PCB layout.
 
#17
The kit allows a person to use a CPLD. It contains all programming hardware and the USB cable, as well as the software. So a person can learn about CPLDs with a minimal investment. Since it's fully functional, in fact, you could just use it in a one-off project.

I don't know how it compares to other makers' products.
 
#19
engineer

Can USB cable in the CoolRunner II development kits connect to JTAG connector?
If not, the USB cable can be used only for the kits, not for target board, so I have to buy a programmer to directly connect PC to JTAG on my target board. is this correct?
 

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