The attached figure shows the block diagram of a CPLD based 8x8 LED matrix display.The gray blocks of the figure must be written in VHDL.In this figure I'm using 8to1 multiplexer to convert parallel data of the EPROM to serial because it doesn't need any control signal. Also I'm using 3to8 line decoder as a column select. In the previous posts i send to you VHDL code of 14bit counter please modify it to 17bit counter as shown in the figure. The following is the VHDL code for the 8to1 multiplexer, 3to8 line decoder, and 3input AND gate
-- 8 to 1 multiplexer
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux8_1 IS
PORT
(sel :IN STD_LOGIC_VECTOR(2 downto 0);
d0, d1, d2, d3, d4, d5, d6, d7 :IN STD_LOGIC;
z :OUT STD_LOGIC);
END mux8_1;
ARCHITECTURE behavior OF mux8_1 IS
BEGIN
WITH sel SELECT
z<=d0 when "000",
d1 when "001",
d2 when "010",
d3 when "011",
d4 when "100",
d5 when "101",
d6 when "110",
d7 when "111",
'0' when others;
END behavior;
-----------------------------------
-- 3-to-8 decoder
library ieee ;
use ieee.std_logic_1164.all;
entity decoder is
port (
a, b, c : in std_logic ;
y : out std_logic_vector (7 downto 0) ) ;
end decoder ;
architecture behavior of decoder is
signal abc : std_logic_vector (2 downto 0) ;
begin
abc <= a & b & c ;
with abc select y <=
"00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others ;
end behavior ;
-------------------------------------------------
-- 3 input AND gate
library ieee ;
use ieee.std_logic_1164.all;
entity and_gate is port (
a,b,c : in std_logic ;
d: out std_logic ) ;
end and_gate ;
architecture behavior of and_gate is
begin
d <= a and b and c ;
end behavior ;