Hi again, and
thank you very much guys.
misterT said:
Can't call that statistics really.. but if you have a way to time 3ms intervals then I would trigger the DMA at 3ms rate to transfer everything in the buffer to the larger storage.
well the DMA doesn't pass the entire buffer, but just section of it at a time.
Say the buffer is from address (0) to (10KB-1)
Say the uC writes to the buffer from (o) to (3KB-1).
Now the DMA starts transferring data of (o) to (3KB-1).
The uC of course continued writing from (3KB) to (6KB-1).
Now the DMA needs to starts transferring data of (3KB) to (6KB-1).
I think I should pass only known-sized sections from the 10KB buffer to the 1MB buffer, because the writing to the 1MB buffer is also done in Cyclic mode.
Therefore I should transfer known-sized sections, which 1MB is dividable by them.
misterT said:
Hard to say without knowing how the buffer is implemented. Calculate how much data is in the buffer and after some limit trigger the dma.
The buffer is simply a static array.
It's starting address and size are known post linkage.
each task writes different amounts of data to the 10KB buffer each time (no constant writing pattern, as it's a real-time application).
I write to the 10KB buffer in cyclic mode.
misterT said:
Calculate how much data is in the buffer and after some limit trigger the dma.
That's exactly the thing - how to calculate when to trigger the DMA, efficiently.
If I add an 'if 10KB buffer reached limit' EVERY TIME I write a log to the 10KB buffer, that could be waste of time, IF there's a more efficient way of course.
NorthGuy said:
So this is just for debugging in case the system crashes?
Mostly, yes.
NorthGuy said:
Usually you do not want to work hard to optimize your debugging because it's going to be removed from production anyway.
Actually it is very important, because without the ability to debug your failures, your product will not be mature enough nor market ready.
It has high value and needs to be optimized in order not to interrupt with the 'normal' work of the system.
The processor you use is probably fast, since you run so many threads. If you're called every 10us on 100MHz processor, it's one write every 1000 cycles. Initiating DMA, will probably take no more than 10 cycles, 1% overhead. If your system cannot take that, it's a problem in itself.
I'm not sure what you're suggesting.
Are you suggesting to trigger the DMA after every write?
It'd be a waste to trigger the DMA every time I write few bytes to the 10KB buffer.
My main problem is, how to efficiently decide when to trigger the DMA?
And base on what to make that decision?
What's the algorithm you'd recommend friends?