I'm not sure whether the following scheme is valid:
As now, instead of having the input to be steady for Tsetup before the clock's rising, it needs to be steady for Tsetup + T(OR_GATE).
(Where T(OR_GATE) is the time it takes to the OR gate to output a valid value).
For that circuit, once the DFF Q output goes high after the CLK pulse due to a logic one on the input, it will stay high independent of the further state of the input. Is that what you want?
As I said, your circuit will output a "1" and then stay at "1" until reset or the power is removed. But if it inputs to a differentiator that may be ok.
To do as you want, you could change the OR gate to an AND gate and add a latch between the FF output and the input to the AND gate.
As I said, your circuit will output a "1" and then stay at "1" until reset or the power is removed. But if it inputs to a differentiator that may be ok.
Below is a simulation using a 4013 dual-D FF to generate only one output pulse with the input goes high (the Space switch). I used the second FF as a latch.
Note that all unused inputs must be connected to ground, which I did not show. Also you will need a signal to initialize both FF's in the desired state when powered up (CD1 and CD2 momentarily high, then low, which could be done with an RC circuit).
Don't know what that means. As my simulation shows you get one pulse out when the input goes high. After that it makes no difference what the input does.
Don't know what that means. As my simulation shows you get one pulse out when the input goes high. After that it makes no difference what the input does.