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Configuring power planes on a 4-layer PCB

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Generally for chips with analog and digital, such as DACs and ADCs, you want a split plane ground plane on the same side as the chip with the digital ground plane on the digital side of the chip and the analog ground on the analog side of the chip, particularly if the chip has a separate analog and digital ground.
The single point connection between the grounds should be through a ferrite bead near the chip(s) if possible.
The ferrite chip you show looks okay although one with a higher impedance at frequency might be better.
 
Generally for chips with analog and digital, such as DACs and ADCs, you want a split plane ground plane on the same side as the chip with the digital ground plane on the digital side of the chip and the analog ground on the analog side of the chip, particularly if the chip has a separate analog and digital ground.
The single point connection between the grounds should be through a ferrite bead near the chip(s) if possible.
The ferrite chip you show looks okay although one with a higher impedance at frequency might be better.

Thanks Zapper for your input, that's the problem here, 7533 has digital pins on both sides and it doesn't have digital gnd input. I will try to put some ferrite beads above and below AD7533 connecting both gnds and use beads with high impedance.
 
Thanks Zapper for your input, that's the problem here, 7533 has digital pins on both sides and it doesn't have digital gnd input. I will try to put some ferrite beads above and below AD7533 connecting both gnds and use beads with high impedance.
You should make only one connection between the planes.
 
Thanks for your observations Cicero

I had two decoupling caps on couple of ICs in digital side (ex: U4, U6), but I can add one more on all other ICs in digital section. Glad you mentioned about routing power lines to ICs, I followed this very carefully when routing so that the power goes to caps first and then to IC power pins.

Both power and gnds are going through ferrite beads, but I am still abit unsure about the value of the ferrite beads that I have to use. My digital signal has a max of 16KHz frequency signals while my analog section has at max 20Mhz signals. At present I am using this variant.

This is one thing that I am unsure of, some say if these are signals that are going to a DAC, its fine and some say the otherway araound. In this case, my U7 is a DAC (AD7533KRZ) and U6 is 74VHC4040M. What would be your recommend here?

thanks again.
Ok, I see them. Do you not need for any for all the other IC's? The routing isn't too bad, but for the ground connection to the caps and device, you're dropping vias to your plane, which means you now have that added via inductance in the path. This is not particularly bad I guess, because your loop is pretty small, I just like to avoid vias in my designs for the decoupling specifically. I'd rather drop vias for the signal lines.

I think its fine with your ferrite beads, as long as you have a footprint there for them you have options. Say if you're doing emissions testing for example and you see issues at 50Mhz, you can easily just pick a ferrite bead that kicks in better at 50Mhz, and you might be ok.

I agree with crutschow, the upper end of U7 is analog, and the lower is all digital. Best of both worlds is to straddle the poly pours, and connect the gnd close to the IC.

I dunno, perhaps connect your gnds (of the two sections) in a start point, just to the right of FB10 at the top. So move both gnd ferrites for your two sections connecting to the power supply right there at the top next to each other. Then move your U7 as close to the top as you can as well, straddling the two sections - so the ass end in the digital side, and the analog end in the analog side. Could minimise loops quite nicely.
 
Thanks crutschow & Cicero for your tips, I updated the layout by straddling both ground planes underneath the DAC and moved the GND beads close to each other (FB11 & FB2). Attached is the updated layout.

Ok, I see them. Do you not need for any for all the other IC's? The routing isn't too bad, but for the ground connection to the caps and device, you're dropping vias to your plane, which means you now have that added via inductance in the path. This is not particularly bad I guess, because your loop is pretty small, I just like to avoid vias in my designs for the decoupling specifically. I'd rather drop vias for the signal lines.

As for the above observation, I tried not to connect IC's gnd pins to GND vias directly rather tried to connect to GND islands around them and connect the islands itself to gnd plane using vias. Do you think that's fine? You said "The routing isn't too bad" which makes me think that I can better is to some extent, please let me know if you have more suggestions/tips.

thanks
 

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Hi Pavan,

Disclaimer: I'm going to be honest here, and just say that although I do this for a living professionally, whatever I say is just my opinion - be it influenced by several years of experience. And like others have said, you get many differing opinions from different professionals about the same thing sometimes - and I'm still learning just like you, and will continue to learn until I kick the bucket.

No, connecting to islands will increase your loop size. What I mean with eliminating vias around the decoupling, is to rather do something like this:
icPowerRouting.jpg
Then you pour your polygons/planes over that. It means your decoupling loop between the caps and your IC is the smallest possible, no vias in between the caps and the pins meaning your cleanest signal with the least inductance as well.

I like your improved layout with the DAC, however the split plane is still a problem in my eyes because of your single gnd pin on the DAC - however I suspected this. You have taken great care to separate your grounds, which is the absolute right method.....to begin with. Now I say, right at the end....remove the split ground pours, and combine them into one. This is good mixed signal pcb design. Yes you cannot do this with ferrite beads on the gnd returns, so rather remove your gnd ferrites - in my opinion.

I dont like a split ground plane, because you need to be ridiculously careful, and 99% of the time you just introduce much larger loops in your design.
My general rules are :
  1. Start with separated grounds to help you separate your digital signals, and analog signals
  2. Take care to put all digital sections over the digital gnd pour, and analog over the analog gnd pour
  3. Remove the split plane completely
The digital signals will keep to their side, and the analog sections will keep to their side, path of least impedance - preserving your signal integrity - they wont bleed into the other section. It'll be the design with the least inductive issues as well.
 
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First of all, without a schematic and some sort of description it is really hard to say anything.
But either way I am not really sure I understand your stack up, so the red is top, blue is bottom, and somewhere unseen is the remaining two?
Those connectors look like RF, what kind of frequencies are you using? Are they terminated? Did you calculate the impedance of the stripline? My guess is that if you have 1.6mm between the thin trace and gnd plane it will be way too high.
 
Hi Pavan,

Disclaimer: I'm going to be honest here, and just say that although I do this for a living professionally, whatever I say is just my opinion - be it influenced by several years of experience. And like others have said, you get many differing opinions from different professionals about the same thing sometimes - and I'm still learning just like you, and will continue to learn until I kick the bucket.

No, connecting to islands will increase your loop size. What I mean with eliminating vias around the decoupling, is to rather do something like this:
View attachment 92178
Then you pour your polygons/planes over that. It means your decoupling loop between the caps and your IC is the smallest possible, no vias in between the caps and the pins meaning your cleanest signal with the least inductance as well.

I like your improved layout with the DAC, however the split plane is still a problem in my eyes because of your single gnd pin on the DAC - however I suspected this. You have taken great care to separate your grounds, which is the absolute right method.....to begin with. Now I say, right at the end....remove the split ground pours, and combine them into one. This is good mixed signal pcb design. Yes you cannot do this with ferrite beads on the gnd returns, so rather remove your gnd ferrites - in my opinion.

I dont like a split ground plane, because you need to be ridiculously careful, and 99% of the time you just introduce much larger loops in your design.
My general rules are :
  1. Start with separated grounds to help you separate your digital signals, and analog signals
  2. Take care to put all digital sections over the digital gnd pour, and analog over the analog gnd pour
  3. Remove the split plane completely
The digital signals will keep to their side, and the analog sections will keep to their side, path of least impedance - preserving your signal integrity - they wont bleed into the other section. It'll be the design with the least inductive issues as well.

Updated the design as suggested in your picture and combined both GND planes. GND from the power is connected only via one bead, FB2 now near the DAC. Added a 10uF along with 0.1uF for all power pins on digital side ICs. I appreciate anymore suggestions you have.

thanks
 

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  • Rev1_2.pdf
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First of all, without a schematic and some sort of description it is really hard to say anything.
But either way I am not really sure I understand your stack up, so the red is top, blue is bottom, and somewhere unseen is the remaining two?
Those connectors look like RF, what kind of frequencies are you using? Are they terminated? Did you calculate the impedance of the stripline? My guess is that if you have 1.6mm between the thin trace and gnd plane it will be way too high.

Yes, those connectors are RF (SMB) and my frequencies are from 30Hz to 15.5KHz. All my SMB connectors are 50Ohm terminated. Not sure about your 1.6mm theory though.
 
With guard ground tracks on a single layer board with thru-hole busbars, you can be successful with a single layer board if 50MHz is your maximum analog signal using guarding techniques. and differential signals.

The Japanese do it all the time in Yamaha equipment. Sometimes 2 layers. 4 layers is when you have lots of digital paths to link . one way per layer with at least one ground plane .

Power planes are useful for distributed capacitance and low impedance power in logic that is not ECL or CML.

That being said I have seen 50 layer boards being made for main frames with liquid cooled 4x16 cores
 
Yes, those connectors are RF (SMB) and my frequencies are from 30Hz to 15.5KHz. All my SMB connectors are 50Ohm terminated. Not sure about your 1.6mm theory though.
With such low frequencies you should be ok either way.
The thickness of the board between trace and ground plane matters at high frequencies, because the trace needs to be 50 ohm as well in order to prevent impedance mismatch and reflections. See **broken link removed** and plug in your values.
 
Following the design techniques suggested here (page 12) for precision op-amp, I redesigned my op-amp design as in layout2, which layout you guys suggest is better?

thanks
 

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With guard ground tracks on a single layer board with thru-hole busbars, you can be successful with a single layer board if 50MHz is your maximum analog signal using guarding techniques. and differential signals.

Could you provide any reference to these design practices to read about?

thanks
 
One more thing that I am thinking of is the digital traces width? Would it be better to reduce the digital trace widths to 0.1 from 0.254?

thanks
 
Depends on speed and Zo impedance, with thin board layers they often go down to 0.003" (0.076mm) track and gap over ground plane. or with interleaved grounds without. Depends on supplier quality / capability/ cost/ crosstalk.

It seems your is low tech, low cost, so , supplier qualification and selection for best match is needed. Defects, warp, twist and registration errors, over/under etch, PTH design /fabrication methods. Measling and crazing ... Etc are all factors.
 
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How are we supposed to know when you don´t show a schematic or any other details. A thinner trace might make things worse, might make things better or nothing at all. Really depends on where it is in the circuit and what the circuit does.
 
How are we supposed to know when you don´t show a schematic or any other details. A thinner trace might make things worse, might make things better or nothing at all. Really depends on where it is in the circuit and what the circuit does.
No problem, here you go... digital section schematic
 

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Can I modify the board such that the bottom layer will run my power traces (+5VDC, +/-5VDC, +/-15VDC) while I have a soloid GND plane in one of the middle layers and have traces on the top (with occasional vias to bottom layer) and use ground pour everywhere there are large empty spaces on top and bottom layers? Is this a good practice?

thanks
 
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