PWR_OK is a “power good” signal. It should be asserted high by the power supply to
indicate that the +12 VDC, +5VDC, and +3.3VDC outputs are above the under-voltage
thresholds listed in Section 3.2.1 and that sufficient mains energy is stored by the converter
to guarantee continuous power operation within specification for at least the duration
specified in Section 3.2.11, “Voltage Hold-up Time.” Conversely, PWR_OK should be deasserted
to a low state when any of the +12 VDC, +5 VDC, or +3.3 VDC output voltages
falls below its under-voltage threshold, or when mains power has been removed for a time
sufficiently long such that power supply operation cannot be guaranteed beyond the powerdown
warning time. The electrical and timing characteristics of the PWR_OK signal are
given in Table 13 and in Figure 6.
Table 13. PWR_OK Signal Characteristics
Signal Type +5 V TTL compatible
Logic level low < 0.4 V while sinking 4 mA
Logic level high Between 2.4 V and 5 V output while sourcing 200 μA
High-state output impedance 1 kΩ from output to common
PWR_OK delay 100 ms < T3 < 500 ms
PWR_OK risetime T4 ≤ 10 ms
AC loss to PWR_OK hold-up time T5 ≥ 16 ms
Power-down warning T6 ≥ 1 ms