and the poster mentioned, causes S to go high for some ns and then go because of delay in leftmost and gate.
Initially, the inputs are lo. the complementary input of the right most gate is actually hi. at the switch turned to hi, because of the propagation delay of some ns of the left most gate, the complementary input is still hi for some ns while A changes to hi. so the output S stays hi for some ns. when the input of the left most gate propagates to the output, the complementary input becomes lo and thus, S becomes lo until the change of status.