Combinational logic circuit input withdrawal

[charlesli]

How will the output of a combinational logic circuit change once the input is withdrawn? It will definitely change, how will it change?

 

[Diver300]

It depends on the type of logic circuit. TTL or LSTTL inputs go to a high logic level if disconnected. Modern CMOS circuits take just about no current so the input behaviour is unpredictable if disconnected.

It is generally a bad idea to leave logic input disconnected. Even if the corresponding output is not used, the current consumption of the circuit can change unexpectedly, and noise can be generated if the input voltage changes.

The voltage, and logic level, of an unconnected CMOS logic input can be affected by current leakage due to moisture, and pickup of electrical signals.

 

[charlesli]

It depends on the type of logic circuit. TTL or LSTTL inputs go to a high logic level if disconnected. Modern CMOS circuits take just about no current so the input behaviour is unpredictable if disconnected.

It is generally a bad idea to leave logic input disconnected. Even if the corresponding output is not used, the current consumption of the circuit can change unexpectedly, and noise can be generated if the input voltage changes.

The voltage, and logic level, of an unconnected CMOS logic input can be affected by current leakage due to moisture, and pickup of electrical signals.

Okay, I get it, thanks a lot!

 

[KeepItSimpleStupid]

A UN2003 can be left unconnected. It's not really a logic circuit.

This part is useful, because when a processor power up, ususlly the I/O is configured as an input, There would be no glitches during power up. Then the port is configured for output. When dsconnected, the state doesn't change either.

CMOS tends to oscillate.
TTL floats high.