Clock pulsing on i2c data bus

[Steve311]

Hi All, When using a i2c communication bus and the master provides a serial clock.. Does this pulse train have to maintain a frequency throughout the start, Sr, ACK and NACK sequence? Or is pulsing the clock (along with data) Ok at any time as long as it is sent in the proper order?

Thanks!

 

[ronsimpson]

The clock does not have to maintain a constant frequency. The data can happen at a different rate than instructions. The ACK could be much slower. There is a maximum frequency but really no minimum frequency.

If the I2C is in hardware you will have a stable clock. I think you are doing thins in software and you will have a clock that is not constant.

Proper order is really important.

 

[Steve311]

Thanks for the help ron. Once I address the slave and provide a clock pulse, for every bit sent, I should be able to release the DATA line (set high), then change my data pin to an input...and test the pin for the slave to pull it low (indicating ACK), Correct?? I am stuck at the first ACK after addressing the slave.

I have an o-scope so I verified the my start bit and slave address, but after that I do not see the data line get pulled low... Any thoughts?

And yes, I am doing this in software.

Thank you again for your help

 

[ronsimpson]

On a real I2C bus the silicon (micro and slave) pull low and do not pull high. A pull up resistor pulls high. (also known as open collector)

If you only have one master then the clock can be driven high and low.

During ACK the micro should set the data pin to input. The pull up resistor pulls the pin high and the slave will pull it low. When you say "should be able to release the DATA line (set high), then change my data pin to an input..." the part "release the DATA line (set high)" I don not understand.

Things to look for. Many slave parts have A0, A1, A2 pins used to change the parts address.
I hope you are not driving the data high during ACK.
If you don't get a ACK from the salve it is not addressed.

 

[Steve311]

Yes, the accelerometer I am working with can have only 2 different addresses.

Maybe that is part of my issue. I am setting DATA high, then changing to an input for ACK pulse. Should I not be driving this line high? And I assume the clock remains high during the ACK?

 

[Pommie]

Here is my soft send byte routine that may be of help.

I2cSendByte	movwf	I2cTemp
		bsf	STATUS,C	;ensures Data isn't zero until 8 bits sent
OutLoop		bcf	SCL		;clock low
		rlf	I2cTemp,f	;move bit to carry flag
		bcf	SDA		;set data low
		btfsc	STATUS,C	;was bit 1
		bsf	SDA		;yes data high
		call	DelayHalf	;10 cycle delay
		bsf	SCL		;clock high
		call	DelayHalf
		bcf	STATUS,C	;ensure 0 shifted into temp
		movfw	I2cTemp		;data = 0x80
		xorlw	0x80
		btfss	STATUS,Z
		goto	OutLoop		;no, keep going 
;GetAck
		bcf	SCL		;pull clock low
		bsf	SDA		;release data
		call	DelayHalf
		bsf	SCL		;release clock
		bcf	STATUS,RP0	;B0, look at port b
WaitSCL		btfss	SCL		;is clock stretched
		goto	WaitSCL		;yes, wait
		call	DelayHalf
		bcf	STATUS,Z	;return z=0 if NAck
		btfss	SDA
		bsf	STATUS,Z	;return z=1 if Ack
		bsf	STATUS,RP0
		return			;in bank 1

Some important notes,
1. the routine is called with RP0=1 (I.E. bank 1 of SFRs selected).
2. SCL and SDA are defined as TRISSx,n - I.E a triss bit.
3. The port bits are assumed to be zero so when TRISSx,n is clear the port will be pulled low.
4. There are 4.7k resistors from the pins to Vdd.

HTH

Mike.

 

[Steve311]

Thanks Mike, Looks like great help. A few questions:
1) Why do you delay 10 cycles after setting the bit? What is the relevance of this?

2)When you release the DATA line, you are essentially driving it high?

3)You set the DATA line low before it tests if the output bit is high or low? And if it is high you pull it high, and if low, you remain the same? Is the i2c bus looking for a rising/falling edge or just a logic level?

Thanks Mike,
Steve

4)I do have 2.10kohm resistor pulled up to Vdd. This should be efficient enough I assume for a PIC?

 

[ronsimpson]

Steve311,

You can not: set high, set low for the clock.
The clock must be slow. 100khz or 400khz.
It looks like Pommie does: set high, delay, set low, delay. Where delay + delay = 100khz.