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Circuit with transistors and diodes

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user

New Member
I need help with the following question:

For the circuit in attach 1, determine the logic function and minimum resistance value of the resistor Rcmin such that the output transistor is in saturation state when it is on.
If the output transistor is charged with capacitor Cp=220nF, determine the fall and rise time of the output voltage.
Given data: βmin=50, β=100, Vcc=5V, Ubet=0.5V, Ubes=0.7V, Ube=Ud=0.6V, Uces=0.2V.

Note: This is not homework, I am practicing for exam.

Attempt:
We consider the static analysis of a circuit (low and high logic level).

Note: I assumed that diodes are idealized (when it is forward biased the voltage is 0.6V, and when it is reverse biased, it is an open branch).

1. Low logic level (Vin=0V)
We don't consider this case because we can never have Vin=0V.
Is this correct?

2. High logic level (Vin=Vcc=5V)
We conclude that at least one input diode is forward biased.
Fourth diode (that is connected to emitter of input voltage) is reverse biased.
Output transistor is on. We need to check if it is in saturation state.
The condition is Ics>Ib/βmin. We can find Ib as Ib=Ubes/5k=0.14mA and Ics as Ics=Uces/Rcmin. This gives that Rcmin>200/7 Ω.
Is this correct?

Where to connect capacitor Cp and how to find fall and rise time of Vout?
What is the value of Vout in this case?
 

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Colin

Active Member
To start with, the voltage drop across each diode is important as they have been added for a reason.
Allow 0.7v drop across a diode and 0.7v drop across the base-emitter junction of each transistor.
You can assume input as 0v, just to see what happens. Then increase the voltage by 0.7v steps and see when things change.
This is why you have to get rid of a University or text book training because it will mess you up completely.
 

audioguru

Well-Known Member
Most Helpful Member
Beta is not used for a saturated transistor. Beta is used only when a transistor is a linear amplifier. Datasheets for most transistors show the saturation voltage when the base current is 1/10th the collector current even when the transistor has a very high beta. Maybe your teacher or text book does not know this.
 

spec

Well-Known Member
Most Helpful Member
I need help with the following question:
Where to connect capacitor Cp and how to find fall and rise time of Vout?
What is the value of Vout in this case?
Hi User,

I have chosen to answer the easy part- the rest of the circuit functions make my head hurt due to the arcane design and the bad wording of the questions.

The capacitor can be connected across the 5K resistor or it can be connected from the collector of the second transitor to 0V; it makes no difference, but you would have thought that this would have been made clear by the exam question.

The output wave form can then be derived as follows:
(1) when the second transistor turns off: from the exponential function for a capacitor and the 5k resistor in parallel.
(2) when the second transitor turns on: from the formula for a capacitor and 5K resistor in parallel being fed by a constant current, the constant current being Ib * beta of the second transistor.

From this you can see that the waveform at the second transistor collector will be asymmetrical with different rising and falling edges. This is a common characteristic with circuits that rely on a resistor to supply current in one of the output directions. So, in your circuit, you will relatively fast falling edges but slow rising edges.

It would be a big help if you could name each component: R1, R2, Q1 and Q2 etc.

It is worrying that such a bad design, as you show, should be an exam question.

You could achieve the same NAND function with one transistor rather than two. Why there is negative feedback on the base of the first transistor is a mystery- it shows confused thinking.

spec

PS: By the way, 0.6V is a perfectly reasonable assumption for the forward drop of a small signal transistor VBE and a small signal diode, assuming both are operating with a low forward current. Some people assume 0.7V, others assume 0.65V and others assume 0.6V. In practice, transistors and diodes of the same type and same circuit conditions, will have varying forward voltages anyway.:)
 
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spec

Well-Known Member
Most Helpful Member
I need help with the following question:
1. Low logic level (Vin=0V)
We don't consider this case because we can never have Vin=0V.
Is this correct?
Hi again User,

I have just realized that there is another easy answer:

No it is not correct that the input cannot be 0V. For example if a relay contact were switching the input to 0V the input voltage would, in fact, be 0V. This would also be the case if the input were from the output of a CMOS gate or from a fully turned on, low RDss, NMOSFET.

Some definitions:

(1) VDrevmax= the maximum reverse voltage of the diodes. For example the ubiquitous small signal 1N4148 diode has a VDrevmax of 75V.
(2) VBErevmax= the maximum reverse voltage of the base emitter junction of the transistors. For example the BC337, small signal switching transistor has a VBErmax of -5V.

So, the most negative input voltage would be, VBErevmax + VDrevmax. In the case of the example components this would be (-5V) + (-75V) = -80V. UPDATE: this is not correct. Please see post #7.
And the most positive input voltage would simply be, VDrevmax. In the case of the example components, this would be 75V.

What this is saying is that with the example components the circuit would operate as intended with input signals of between -80V and plus 75V. Of course, in practice, you would allow a safety margin, of say 20%, so in the specification for the circuit you would state that the circuit will operate normally with an input voltage rang of -64V and 60V.

spec
 
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jjw

Member
When input voltage is negative the input diode is forward biased and max negative voltage is about -4.3V.
I am not sure if it was even asked.
 

spec

Well-Known Member
Most Helpful Member
Hi jjw
When input voltage is negative the input diode is forward biased and max negative voltage is about -4.3V.
I did make an error but so did you.

The lowest input operating voltage will be 0.6V (forward drop across the input diode) plus the voltage collector base max of the first transistor (the diode on the emitter of the first transistor is reversed biased and thus protects the emitter base junction of the first transistor.

I am not sure if it was even asked.
There is such a thing as a complete and definative answer, especially for a student.

If you are on a mission to point out the areas of posts on ETO that weren't asked, you are going to be fairly busy.:eek:

spec
 
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cowboybob

Well-Known Member
Most Helpful Member
... 1. Low logic level (Vin=0V)
We don't consider this case because we can never have Vin=0V.
Is this correct? ...
Just curious: What is the need or justification for the parameter?

EDIT:
The lowest input operating voltage will be 0.6V (forward drop across the input diode) plus the voltage collector base max of the first transistor (the diode on the emitter of the first transistor is reversed biased and thus protects the emitter base junction of the first transistor.
I see...
 
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