Need to learn how making frequency counter (or any time critical project) using PIC18F that display output over USB.
Having choice of 3 clock sources:
1. ±50ppm 4.0000 MHZ crystal ATP040SM
4.0000 MHZ 20PF SMD ±50ppm
https://www.electro-tech-online.com/custompdfs/2011/08/008-0325-0_A.pdf
2. ±50 ppm 24.0MHZ external oscillator
XO-54D-24.0MHZ
±50 ppm
**broken link removed**
3. ±100 ppm 40.0MHZ external oscillator
MXO45-40M000 Manufacturer: CTS CORP
40 Mhz
±100 ppm
https://engineering.dartmouth.edu/courses/engs031/databook/oscillator.pdf
To run internal PLL PIC18F will divide clock input by PLLDIV that can be setting to either 1, 6 or 10 for above options respectively.
I thinking which option providing best stability?
When thinking myself, I feel 3rd option will be best as I reasoning that ±100 ppm 40Mhz clock will be divide by 10 and hence effectively behaving like ±10 ppm 4Mhz clock?
Or is reasoning wrong and ±100 ppm 40Mhz clock after divide by 10 is effectively still ±100 ppm 4Mhz clock?
If you, experienced designing having choice of above 3 - which one you choose and why (no consider PCB space or 5V voltage issue in 3.3v world, but might consider cost only between more expensive ±50 ppm vs less expensive ±100 ppm)
Having choice of 3 clock sources:
1. ±50ppm 4.0000 MHZ crystal ATP040SM
4.0000 MHZ 20PF SMD ±50ppm
https://www.electro-tech-online.com/custompdfs/2011/08/008-0325-0_A.pdf
2. ±50 ppm 24.0MHZ external oscillator
XO-54D-24.0MHZ
±50 ppm
**broken link removed**
3. ±100 ppm 40.0MHZ external oscillator
MXO45-40M000 Manufacturer: CTS CORP
40 Mhz
±100 ppm
https://engineering.dartmouth.edu/courses/engs031/databook/oscillator.pdf
To run internal PLL PIC18F will divide clock input by PLLDIV that can be setting to either 1, 6 or 10 for above options respectively.
I thinking which option providing best stability?
When thinking myself, I feel 3rd option will be best as I reasoning that ±100 ppm 40Mhz clock will be divide by 10 and hence effectively behaving like ±10 ppm 4Mhz clock?
Or is reasoning wrong and ±100 ppm 40Mhz clock after divide by 10 is effectively still ±100 ppm 4Mhz clock?
If you, experienced designing having choice of above 3 - which one you choose and why (no consider PCB space or 5V voltage issue in 3.3v world, but might consider cost only between more expensive ±50 ppm vs less expensive ±100 ppm)
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