My problem is related to the capacitve coupling between the gate and the drain of the IXT03N400 FET that I am using as a switch. Whenever I apply 12 V to the gate of my FET, the voltages at the drain first goes up. This increase in voltage is visible as a positive spike on my oscilloscope. After that spike the voltage between drain and source collapses as the n-channel FET becomes conductive.
I am trying to develop an application where I need to switch voltages between 1.7 V and 300 V within a maximum of 60 ns. In other words, I apply 12 V at the gate in order to switch voltages between 1.7 V and 300 V. The voltage is supplied by a commercially available flyback converter (Traco MHV).
Those positive voltage spikes at the drain electrode of my FET are unacceptable within the context of my application. Any idea of how I can ressolve this issue?
I am trying to develop an application where I need to switch voltages between 1.7 V and 300 V within a maximum of 60 ns. In other words, I apply 12 V at the gate in order to switch voltages between 1.7 V and 300 V. The voltage is supplied by a commercially available flyback converter (Traco MHV).
Those positive voltage spikes at the drain electrode of my FET are unacceptable within the context of my application. Any idea of how I can ressolve this issue?