You're kinda missing the point.. He needs non volatile parallel ram to replace the SRAM... SPI or I2C isn't what's required..
gotcha, ( obviously I missed your threads)
Vbat backup is pretty simple with diode logic and higher voltage supplies the current.
THe reliability is ensured with a low ESR cap on the chip to prevent transients and careful examination of CE or chip enable during power down to prevent illegal writes. So at minimum all you need is a pair of Schottky diodes and a good cap. THe battery can be carefully selected knowing the static current.
Coin Cells used tend to have 3k series resistance, but CR123 Lithium Cells are << 1Ohm. which could last years. You can measure standby current using Ohm's Law, V/R=I current with 100 Ohm series resistor or similar to the chip and low leakage cap to drop at least 50mV.
A simple transistor to disable CE ( wired OR PNP if active low) from sensing the bus voltage not present by sensing.
It's not that complicated. ASk for more details after you make a measurement on current.
BTW a CR123 battery has hundreds of Farads and is cheap compared to a super cap and exactly 3.0V
I suspect your SRAM is rated for a voltage range of 2.7V to 5.5V and uses < 1uA in standby mode. You can also disable WE instead of CE with a pull up R.
Be careful about enabling the chip while the game PCU has no power as CMOS latchup can occur when you apply power and the signal voltages from SRAM are higher than the BUS chips powered down. THis is a well know phenomenon that burns up the chip in an SCR latchup mode for CMOS. It may only just get warm or hot depending on vintage of chip, so CE disables the signals to float on the bus when power OK goes low. N.B. look for Power OK signal or make one so you avoid applying bus voltages (tri-state mode) from SRAM when other devices are powered down.
Vcc must go high before any signals on the bus from SRAM.