Continue to Site

Welcome to our site!

Electro Tech is an online community (with over 170,000 members) who enjoy talking about and building electronic circuits, projects and gadgets. To participate you need to register. Registration is free. Click here to register now.

  • Welcome to our site! Electro Tech is an online community (with over 170,000 members) who enjoy talking about and building electronic circuits, projects and gadgets. To participate you need to register. Registration is free. Click here to register now.

Build logic analyzer

Status
Not open for further replies.
The great thing about programmable logic is that you don't need your soldering iron to make changes. You can also put all your logic into one chip. If you can come up with a simple counter circuit that will do what you need you might as well do that but a CPLD is more flexible- it makes your hardware design like software design. I'm having a great time working with VHDL (a programming language to design digital logic) so I'm a bit partial to programmable logic right now.

SRAM is fairly easy to use. The timing can be a bit confusing because its asyncronous but it shouldn't be too bad.

If you want to see what working with CPLDs and FPGAs is like Xilinx has free design software for all their CPLDs and most of their FPGAs. Its called ISE Webpack and you can download it from their site.
 
I worked one year with VHDL. It helps to start with CPLDs ??

Anyway, for this task I think a 74LS161 counter will do... At least for SRAM addressing. The problem is now stop the counters when RAM is full (some AND gates would do) and let a paralel port take out the data.
 
To take a non-stop sampling trough paralel port I'm thinking of using a shift register, that shifts bits into it at 2Mhz, for example, and then paralel output to an 8 bit paralel port data bus, at 250Khz, speed that can achive EPP or ECP (so all 8 last sampled bits come in at a time).
It's also an idea.
 
If you know VHDL Doing your project with a CPLD would be easy. You can program all your logic, in VHDL, into the CPLD and not have to deal with any other IC's. You can program the counter, shift registers and gates all into a single CPLD. Xilinx' free software lets you design in VHDL, Verilog or schematics.
 
patroclus said:
I worked one year with VHDL. It helps to start with CPLDs ??

Anyway, for this task I think a 74LS161 counter will do... At least for SRAM addressing. The problem is now stop the counters when RAM is full (some AND gates would do) and let a paralel port take out the data.

I strongly suggest you use a programmable part like a CPLD as has been suggested. As you go through the design, you will realize you need more logic than just the counters & shift registers etc... One cpld will be much cheaper than all of the cheap discrete logic you're thinking about. And as was pointed out, you will need to be making lots of changes as you design and test. Make your life easy to start out with... CPLD is cheap and software is free.. you can't beat that!
 
patroclus said:
any good place to start working with CPLDs??

Download the ISE webpack from xilinx. With this tool, you can create a logic schematic or write VHDL (a few other source input metods as well) and target something like the 95xx series of cplds. You can even get a free model sim simulator that will simulate the VHDL up to 500 lines of code worth. After you have picked your SRAM part, try writing the interface for it and simulate it.. I think that would be a great way to get your feet wet.
 
Ok, I'm on it.
Are there any other choices appart from xilnix??

and one more thing.. isn't it better to use a 74LSxxx counter instead of program a counter on a CPLD, and better use the CPLD for all the logic appart from it??
If you can design circuits using VHDL and so, I imagine there will be a big library of circuits ready to program on a CPLD, am I wrong??
 
There are a bunch of CPLD manufacturers. Altera is another big manufacturer. They also have free design software.

If you put a CPLD in your project you might as well put the counter into the CPLD. There is no reason to have a separate counter chip. There is tons of information about Coding VHDL for CPLDs on the internet. If you do a search for VHDL and counters you will find tons of code to implement them. Both Xilinx and Altera have standard libraries for counters and other components if you want to use them but its probably easier to just write them in VHDL than try to find the right library part.
 
Data Logger the easy way

Now I can't be accused of advertising ...
EBay just sold a Thandar LA160 data logger (upto 10MHz sample rate) complete for just £21.50 + £5.00 postage.
You will work hard to beat that for a cheap and easy solution to your problem ...

search EBay for item number 3834498548
 

Attachments

  • thurlby_la160_v2.jpg
    thurlby_la160_v2.jpg
    23.9 KB · Views: 348
Re: Data Logger the easy way

mechie said:
Now I can't be accused of advertising ...
EBay just sold a Thandar LA160 data logger (upto 10MHz sample rate) complete for just £21.50 + £5.00 postage.
You will work hard to beat that for a cheap and easy solution to your problem ...

search EBay for item number 3834498548

Of course! I'll tell ya.. over the years, I have seen some fantastic deals come and go on ebay for electronics equipment.. Alot of it is certified junk though (in most cases the seller doesnt even know it!) But there is plenty of good stuff to be had.

I had been under the impression that the original poster was wanting a learning experience though, by making his own since 8MHz isnt so fast that you can't get away with a crude design. My Grandmothers logic analyzer is faster than 8M sample rate so I assume he would have bought one (10Meg or better) by now if he was so inclined...

_or_ he's been hiding in the basement all these years and doesnt know about ebay!
 
Status
Not open for further replies.

Latest threads

New Articles From Microcontroller Tips

Back
Top