EISA appears to be a simple non-multiplexed bus & I believe XMS is just continuous RAM area beyond the 1MB point?
As far as I can see from a quick look, all it needs is basic buffering and decode to start at memory address zero, but omitting (not enabling the data bus buffers for read, at least) the area of RAM on the motherboard so there is no conflict.
As long as it's seen as a continuous block with the onboard RAM by the BIOS memory test, I think it should just work?
(You could offset the entire address range to start it above the onboard RAM, but omitting something from 1 - 16MB out of 4GB seems a lot simpler and pretty irrelevant!)
You may have to take care of Dynamic RAM refresh yourself, though.
I remember problems with older systems, ISA / PCI at least, as they only had a limited number of bits in the internal refresh address counter for automatic DRAM refresh, and newer DRAM ICs that needed more bits in the refresh address did not work.
I've not done anything with DRAM design-wise for decades though, so it may well be that the RAM has an internal refresh counter and only needs regular refresh triggers?