I've been working my way through this schematic. I understand pretty much the whole thing except for the leg connected to node 3. Is this some kind of biasing network? That would make sense, but I don't understand the capacitor in there (the 10uF one), or why it's so complex in general. Seems like a simple voltage divider would do.
Yes, it's to bias the chip - effectively providing a split supply off of a single supply. The 10uF is to decouple that supply, as any supply needs, and you can't connect it directly to the chip as it would short out the input - the 1M resistor actually sets the input impedance for the circuit.