FPGA’s and power efficient applications are not something that go together usually, FPGA’s can be very current hungry with large designs.
Anyway analogue processing in an FPGA is usually done with the following system. ADC (Analogue to Digital Converter) -> FPGA -> DAC (Digital to Analogue Converter). ADC converts the continuous analogue waveform into a discrete time n bit number where range of the number is 0 to 2^n. This a fractional number where it represents voltage as of ADCnumber * ( Vreference/2^n). Where Vreference is a full scale reference voltage you will supply to the ADC.
You can then do control loops, filters or anything you wish to do mathematically with this number (for example a basic digital filter is basically a dot product Ʃax ) and then output this binary number to a DAC where it will be reconstructed into an analogue signal.
Only other I would like to recommend is you make yourself aware of aliasing, basically you will get nonsense results from your ADC if your input signal has a frequency > ½ of your ADC sampling frequency.