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;*************************************
; Author : Mike Baird
; Program : ADC Example, Takes ADC result from AN0 and display LSB on PORTB
; Date : September 7th, 2009
;*************************************
List P=16F88
#include "P16F88.INC"
__CONFIG _CONFIG1, _PWRTE_ON & _WDT_OFF & _INTRC_IO & _BODEN_OFF & _LVP_OFF & _CP_OFF & _MCLR_OFF
__CONFIG _CONFIG2, _IESO_OFF & _FCMEN_OFF
;*** Cblock ***
CBLOCK 0x20
d1
d2
ADCLOW
ADCHIGH
ENDC
;*** START OF RAM ***
ORG 0x000 ; Start of program vector
GOTO Start ;
ORG 0x004 ; Interrupt vector
;*** ISR ***
RETFIE
;*** Configuration ***
Start
CLRF PORTA ; PortA all low
CLRF PORTB ; PortB all low
BSF STATUS,RP0 ; Bank 1
MOVLW b'01100000' ; Make clock 4Mhz
IORWF OSCCON
MOVLW b'00100001' ; Bit 5 input, Bit 0 for ADC
MOVWF TRISA ; PortA all output except MCLR
CLRF TRISB ; PortB all output
MOVLW b'00000001' ; Set RA0 as analog input
MOVWF ANSEL ;
MOVLW b'10000000' ; MSB on the left (Top 6 bits of ADRESH = 0 )
MOVWF ADCON1 ;
BCF STATUS,RP0 ; Bank 0
MOVLW b'11000001' ; Set ADC input to AN0, clock FAD, turn on ADC
MOVWF ADCON0 ;
;***
Main:
CALL Delay1ms ; Wait MUCH longer then required aquasition time, see below for time
BSF ADCON0,GO
BTFSC ADCON0,GO ; Wait for conversion to be complete
GOTO $-1 ;
BCF PIR1,ADIF
CALL ADCMOVE
MOVF ADCLOW,W ;
MOVWF PORTB ;
CALL Delay
GOTO Main ;
ADCMOVE:
MOVF ADRESH,W ;
MOVWF ADCHIGH ;
BSF STATUS,RP0 ; Bank 1
MOVF ADRESL,W ;
BCF STATUS,RP0 ; Bank 0
MOVWF ADCLOW ;
RETURN
;*** Delay ***
Delay1ms
MOVLW d'6' ; 1 Ms Delay (924 uS)
MOVWF d2
Delay
DECFSZ d1,F
GOTO Delay
DECFSZ d2,F
GOTO Delay
RETURN
;********************
END
; That's all folks!
;*************************************************************************************
;
; Note: On a Power-on Reset, the pins PORTA<4:0> are configured as analog
; inputs and read as ‘0’.
;
;
; ANSEL: ANALOG SELECT REGISTER(ADDRESS 9Bh) PIC16F88 DEVICES ONLY
;
; Bit7 = Unimplemented: Read as ‘0’
; Bit 6:0 = ANS<6:0> Analog Input Select bits
;
; Bits select input function on corresponding AN<6:0> pins.
; 1 = Analog I/O(1,2)
; 0 = Digital I/O
;
; Note 1: Setting a pin to an analog input disables the digital input buffer. The corresponding
; TRIS bit should be set to input mode when using pins as analog inputs. Only AN2 is
; an analog I/O, all other ANx pins are analog inputs.
; 2: See the block diagrams for the analog I/O pins to see how ANSEL interacts with the
; CHS bits of the ADCON0 register.
;
;
; ADCON0: A/D CONTROL REGISTER (ADDRESS 1Fh) b'00000001'
;
; bit 7-6 ADCS<1:0>: A/D Conversion Clock Select bits
;
; If ADCS2 = 0:
; 00 = FOSC/2
; 01 = FOSC/8
; 10 = FOSC/32
; 11 = FRC (clock derived from the internal A/D module RC oscillator)
; If ADCS2 = 1:
; 00 = FOSC/4
; 01 = FOSC/16
; 10 = FOSC/64
; 11 = FRC (clock derived from the internal A/D module RC oscillator)
;
; bit 5-3 CHS<2:0>: Analog Channel Select bits
;
; 000 = Channel 0 (RA0/AN0)
; 001 = Channel 1 (RA1/AN1)
; 010 = Channel 2 (RA2/AN2)
; 011 = Channel 3 (RA3/AN3)
; 100 = Channel 4 (RA4/AN4)
; 101 = Channel 5 (RB6/AN5)
; 110 = Channel 6 (RB7/AN6)
;
; bit 2 GO/DONE: A/D Conversion Status bit
;
; If ADON = 1:
; 1 = A/D conversion in progress (setting this bit starts the A/D conversion)
; 0 = A/D conversion not in progress (this bit is automatically cleared by hardware when the A/D
; conversion is complete)
;
; bit 1 Unimplemented: Read as ‘0’
; bit 0 ADON: A/D On bit
;
; 1 = A/D converter module is operating
; 0 = A/D converter module is shut off and consumes no operating current
;
;
; ADCON1: A/D CONTROL REGISTER 1 (ADDRESS 9Fh)PIC16F88 DEVICES ONLY
;
;
; bit 7 ADFM: A/D Result Format Select bit
;
; 1 = Right justified. Six Most Significant bits of ADRESH are read as ‘0’.
; 0 = Left justified. Six Least Significant bits of ADRESL are read as ‘0’.
;
; bit 6 ADCS2: A/D Clock Divide by 2 Select bit
;
; 1 = A/D clock source is divided by 2 when system clock is used
; 0 = Disabled
;
; bit 5-4 VCFG<1:0>: A/D Voltage Reference Configuration bits
;
; Logic State VREF+ VREF-
; 00 AVDD AVSS
; 01 AVDD VREF-
; 10 VREF+ AVSS
; 11 VREF+ VREF
; Note: The ANSEL bits for AN3 and AN2 inputs must be configured as analog inputs for the
; VREF+ and VREF- external pins to be used.
;
; bit 3-0 Unimplemented: Read as ‘0’
;
;
; These steps should be followed for doing an A/D conversion:
;
; 1. Configure the A/D module:
; • Configure analog/digital I/O (ANSEL)
; • Configure voltage reference (ADCON1)
; • Select A/D input channel (ADCON0)
; • Select A/D conversion clock (ADCON0)
; • Turn on A/D module (ADCON0)
;
; 2. Configure A/D interrupt (if desired):
; • Clear ADIF bit
; • Set ADIE bit
; • SET PEIE bit
; • Set GIE bit
;
; 3. Wait the required acquisition time.
;
; 4. Start conversion:
; • Set GO/DONE bit (ADCON0)
;
; 5. Wait for A/D conversion to complete, by either:
; • Polling for the GO/DONE bit to be cleared
; (with interrupts disabled); OR
; • Waiting for the A/D interrupt
;
; 6. Read A/D Result register pair (ADRESH:ADRESL), clear bit ADIF if required.
;
; 7. For next conversion, go to step 1 or step 2 as required. The A/D conversion time per bit is
; defined as TAD. A minimum wait of 2 TAD is required before the next acquisition starts.
;
;
; EQUATION 12-1: ACQUISITION TIME
;
; TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
; = TAMP + TC + TCOFF
; = 2 µs + TC + [(Temperature -25°C)(0.05 µs/°C)]
; TC = CHOLD (RIC + RSS + RS) ln(1/2047)
; = -120 pF (1 kO + 7 kO + 10 kO) In(0.0004885)
; = 16.47 µs
; = 2 µs + 16.47 µs + [(50°C – 25°C)(0.05 µs/°C)
; TACQ = 19.72 µs
;
;*************************************************************************************
